Common gate wideband RF amplifiers

[A.Z.]

Just stumbled upon a paper (Ham Radio Magazine) dating back to 1979 and dealing with the design of common gate JFET RF amplifiers

https://worldradiohistory.com/Archive-DX/Ham%20Radio/70s/Ham-Radio-197911.pdf

the article starts on page #14 of the PDF (page #12 in the magazine), and while it isn't "special", I believe it may be interesting for anyone willing to design the input stage of a receiver fed using 50Ohm, in particular the designs shown in figures #6 and #7 which give unity or low gain, may be suitable as an input buffer and impedance matching stage for homemade receivers

Again, nothing special, but I hope it may be of interest

[RoV]

Thank you.
Unfortunately, it seems that FET CG amplifiers are relatively noisy, with minimum NF=2..3 dB. I remembered having read somewhere they are not good for LNA, but I couldn't locate the book, so I searched the net and I stumbled upon this interesting lecture: http://rfic.eecs.berkeley.edu/~niknejad/ee142_fa05lects/pdf/lect13.pdf: see in particular the result at page 18.

[David Hess]

I would have said that a 2 to 3 dB noise figure is pretty good for a commonly available part and simple circuit, but at HF and maybe 6 meters, that is more than enough performance because of high levels of background noise.

I would like to see more about how to produce high IP3 and compression for an low noise LNA, but the measured performance is pretty good, although power consumption is high as well.  The designs I remember use a differential two transistor common-base amplifier.

A lot can be learned from old articles like this.

[UR5FFR]

Common gate amplifier have constant input impedance in wide frequency range and good isolation. Its other property is that it can be easily reversed. This makes it possible to build fairly simple transceivers. In the attachment there is a schematic of one of my developments - the Raisin TRX.

[TimFox]

Back around 1990, I used premium JFETs (especially the dear departed 2SK152 from Sony) to get very low noise figures around 10 MHz.
As I remember, the optimum source impedance for low noise figure is almost the same for grounded-source and grounded-gate configurations, although the input impedance in grounded-source is a high resistance with non-trivial capacitance and the input impedance for grounded-gate is roughly 1/g_m, which was approximately 100 ohms for this device.
(Apparently, Sony designed this part for use as a low-noise preamplifier for vidicons, but it was quickly recognized for use in HF receivers.  Neither market sufficed to keep the part in production.)

[thundertronics.com]

Microwave LNA FET manufacturers usually provide small signal S-parameters measurement for common source configuration. If you keep source pin well grounded, on a thin substrate with a closely spaced ground vias, stability region will cover large area over center of Smith Chart and provide stable operation with relatively big mismatch margin. I used to think that anything on a source pin is only useful to create series feedback oscillator. Surprisingly, configuration you've noticed is pretty interesting in GHz range too, I've already found few papers on wideband common gate amplifiers, but what interested me most is common gate electronically tunable matching stage using variable bias. Thanks for sharing.

[T3sl4co1l]

There's no shortage of mm-wave circuitry using cascodes and such (often in distributed amplifiers to get the required BW), but those are specifically monolithic (InP and other) constructions, nothing you'll get as board-level components (and, obviously at that frequency range, with good reason!).

Other than that, I think it doesn't matter too much; the board-level components you do find, have incredibly low Crss, as if internally cascoded.  (In the past, you could get dual-gate MOSFETs of exactly this design, but what passes for "RF transistors" these days is whatever variety of HBT or PHEMT with 30GHz+ fT, made with whatever combination of geometry and formulation that makes that possible.)  So, little neutralization is needed even in common source/emitter, and the maximum stable gain and bandwidth are quite high.  Basically, GG would only make things worse.

And still other than that -- with older more pedestrian types like JFETs, BJTs, and the odd MOSFET that's still around that's not just intended for straight up switching (..are there even any?), you'll have, well I guess an easier time using them at modest frequencies (1-100s MHz) heh, not like having to sweat the fT on the GHz ones -- but also the poorer performance that they give in general, and have to address things like by using GG configuration.

So, given that as a limitation, say -- there are still some newer parts, very slightly improved over the classics; CPH3910 or NSVJ3910 are comparable or better than the (more recently-classic, but mostly now obsolete) BF862.

And yeah, not that incredibly low NF is much of an issue at these frequencies; the main difference is being able to use a smaller antenna -- such that antenna and input stage losses, in terms of Johnson noise, are comparable to received atmospheric noise, thus making the system as small as possible, and requiring just that little bit better NF at the input.  This being most relevant to automotive radios, themselves already a dying breed.

Tim

[David Hess]

Transistors intended for common base and gate circuits use a different pin layout with the emitter/source and base/gate swapped to reduce the impedance at the base/gate as much as possible and increase isolation between the emitter/source and collector/drain.  A TO-39 package would connect the base/gate to the case.  4 pin power packages would have two opposing base/gate pins instead of emitter/source pins.

[G0HZU]

Thanks, that was a well presented article with good info. Dated 1979 it still reads well today. One comment I do have is that it doesn't mention much about RF instability. Common gate (and common base) VHF RF amplifiers are amongst the worst offenders for instability up at UHF unless some care is taken with the design.

[mawyatt]

Here's a very interesting configuration of a type of Cascode that also creates single ended to differential current conversion with a type of class A/B operation. Don't know the exact origin of this configuration but we discovered it in a hand note by Barrie Gilbert as he later used it in early renditions of his MicroMixer.

The design has some unique properties, like handling large input bipolar levels with a unipolar supply, maintaining a controlled input impedance over large input signal ranges, and unlimited current mode dynamic range with ideal transistors. In actual RF usage, select resistors can be replaced with very low Q inductor/resistors to improve the noise figure.

We used this design concept many times with various flavors of IBM SiGe BiCMOS transistors (>400GHz). The intricate details of the controlled input impedance and dynamic range behavior are quite involved and transcendental, however specific values of bias current, and resistor/inductors create very interesting amplifier properties like harmonic "suck out" and gain "expansion" rather than compression.

In the images below note how the collector currents of Q2 and Q4 cross at 0 volts, the input current is somewhat linear from -10 to +10ma and how the difference collector current is also somewhat linear from -10 to +10ma. Also note at zero input level the input impedance is ~ Rinput +[kT/(q*Ibias) + R]/2 and at very high input levels the input impedance asymptotically approaches R1 + R for either input polarity. Of course for RF/MW/MMW use better transistors than 2N3904 would be required.

Edit: Forgot to mention Ibias should be PTAT for temperature compensation of the input impedance.

Anyway, thought this might be of interest to some folks.

Happy Thanksgiving.

Best,

[T3sl4co1l]

Hmm, bears a passing resemblance to this balanced driver circuit I made some time ago:



Seems like the balance (of your simplified / RF-optimized version) would need some tweaking, but also I think I can convince myself that's what the diode strapped part is for?  Impedance would tend to be very low which might not matter for integrated but could be a GBW problem for discrete? 

Tim

[A.Z.]

Thanks, that was a well presented article with good info. Dated 1979 it still reads well today. One comment I do have is that it doesn't mention much about RF instability. Common gate (and common base) VHF RF amplifiers are amongst the worst offenders for instability up at UHF unless some care is taken with the design.

well, the author wrote about applications from VLF up to the "edge" of VHF, and I don't think a proper designed common gate stage could be so problematic at HF and below

[mawyatt]

Hmm, bears a passing resemblance to this balanced driver circuit I made some time ago:



Seems like the balance (of your simplified / RF-optimized version) would need some tweaking, but also I think I can convince myself that's what the diode strapped part is for?  Impedance would tend to be very low which might not matter for integrated but could be a GBW problem for discrete? 

Tim

Yes your circuit does look similar if you just look at the current outputs from the bottom 2 transistors, and seems to be for clock generation and not ultra-linear use due to the Class B outputs?  The circuit we mentioned above (shown below) was from 1980 era, Gilbert used it in his Micromixer later.

However the 3 resistors not shown in your circuit are critical for large signal performance, Rinput, R2 and R4. R5 is just to match R4, but in use should be slightly smaller to match the collector currents from Q2 and Q4 to null the even order harmonics. We used IC traces and in the chips with these resistors to create the effective small difference. Here's an example showing R4 as Rx value of 25.8 vs R4 of 26, note the effect on difference currents between the input and collector Q2 & Q4 differential currents.

Studying the effects of these 3 resistors, or resistor/inductors in actual use for lower noise, is a fascinating undertaking eventually culminating in transcendental solutions. Vaguely remember a post doc student working on this and posting some unique values and ratios between resistors and bias current that had very unique and useful features, like the aforementioned harmonic "suck out" and "gain expansion" characteristics.

With good high frequency transistors like the SiGe device we used, very high Dynamic Range, Broadband from ~DC to 10s of GHz are achievable at modest power consumptions, however one can get very useful results with just about any transistor.

This unique amplifier is certainly easy enough to built and play around with. For those interested in just simulations, recall that MEXTRAM or HICUM bipolar models are required if high fidelity results are expected.

Anyway, nice to see similar type concepts being used as we hadn't seen any other uses of this useful circuit topology outside our own use.

Best,

[G0HZU]

Thanks, that was a well presented article with good info. Dated 1979 it still reads well today. One comment I do have is that it doesn't mention much about RF instability. Common gate (and common base) VHF RF amplifiers are amongst the worst offenders for instability up at UHF unless some care is taken with the design.

well, the author wrote about applications from VLF up to the "edge" of VHF, and I don't think a proper designed common gate stage could be so problematic at HF and below

The problem when using a JFET is that it can oscillate up at UHF (eg 800MHz) when the amplifier has been designed and built for use down on the HF bands. I didn't spot anything in the article that warns against this risk. Maybe the author wasn't aware of this instability risk back in 1979?

[A.Z.]

The problem when using a JFET is that it can oscillate up at UHF (eg 800MHz) when the amplifier has been designed and built for use down on the HF bands. I didn't spot anything in the article that warns against this risk. Maybe the author wasn't aware of this instability risk back in 1979?

I doubt it, my take is that the author scope was mainly to exemplify how to design a JFET "common gate" stage; as for oscillation, in my own experience it mostly depends from how one designs the stage and from how one builds it, for sure most RF stages won't perform as expected if one uses a sloppy design or build

[David Hess]

The only added risk that I am aware of with a common base or gate stage is that a higher operating frequency is possible, and the design texts I have read often list greater stability as an advantage.  In my experience, a common emitter or source design is more likely to oscillate.

But great instability might be a problem when parts designed for common emitter or source operation are used in a common base or gate design.  As I pointed out above, the pin layout optimizes a package for one or the other.

[G0HZU]

Yes, it's the introduction of some inductance at the gate connection that can lead to instability up at UHF.

There will be some resistive damping up at higher frequencies due to the lossy ferrite material used in the 4:1 and 9:1 transformers and this ought to be enough to achieve unconditional stability in most if not all of the designs in that article if built with a sensible layout.

[G0HZU]

I had a go at simulating some of the amplifier circuits using some old s2p files of an MMBFJ310 JFET and the gain was generally a bit lower than the results in the Ham radio magazine article. This is because I only have (12Vds) sdata files at 10mA Id and not 17mA.

Note that the author had to use split +/- 12V supplies to get sensible bias resistor values for these JFETs.

I tried paralleling up two s2p models to get more transconductance (to try and mimic the E430 JFET) and again it fell short on transconductance because each model was biased at just 10mA and not 17mA. So my results for gain were a bit low.

The 4:1 transformers are really transmission line transformers (TLT) and this makes them fairly easy to model even up at UHF. My first attempt at a stability analysis showed that only 4nH of gate inductance was needed to make the parallel JFET model lose unconditional stability with the 4:1 TLT model attached. This was with the 10mA s2p model.

I should have some free time tomorrow and I'll try and get an s-parameter model of the sot-23 MMBFJ310 JFET at 17mA Id and 12Vds. I think the simulated gain results will then agree closer with the amplifier designs in the article. It really is a well written article and hopefully the author produced more like this.

[mawyatt]

Added a plot of input resistance vs input voltage for amplifier mentioned a few posts above. This is computed in LTspice as (derivative of input voltage)/(derivative of input current). By adjusting the bias current and mentioned resistors you can change the shape and range of the input resistance.

Best,

[G0HZU]

Sadly I haven't had much free time but see below for a couple of graphs of K factor for a MMBFJ310 (sot-23 SMD) J310 in common gate biased at 10Vds and 10mA.

This is just the JFET in a VNA test fixture biased using VNA bias tees. The first plot shows K when the gate pin of the SMD package is direct to a ground plane. K is above 1 from about 1MHz to 2GHz.

The second plot shows K when just 4mm of leg inductance is added at the gate and this simulates what you might see from a non-SMD part. You can see that K goes below 1 over much of VHF and UHF. This opens the door to instability. This is just at 10mA Id. It would be a bit worse at 18mA ID and even worse again if two were placed in parallel. This should show that this type of amplifier is really prone to instability up at UHF unless care is take to ensure a short gate connection. If you use the T0 plastic J310 then you really do have to try to cut the gate leg 'really' short and even then I suspect it wont achieve a K over 1 at UHF. However it will help reduce the chance of instability.

The plots below were taken using s-parameter data taken from my VNA in a decent test fixture across LF through to 2GHz.

[G0HZU]

If you explore various transistor types on a VNA like this you can get  some real surprises as to how high up in frequency a part can oscillate. For example the VNA data shows that a jellybean 2N3904 BJT can potentially oscillate above 1GHz when biased at about 15Vce and 10-15mA Ic. Without analysis of the 2N3904 transistor like this using a VNA it would be difficult to know this instability at 1GHz was even possible.

See below for a VNA derived plot of K for a jellybean 2N3904 in common emitter configuration at 10Vce and 10mA Ic. The s-parameter data extracted from my VNA shows that self oscillation of the 2N3904 is possible at over 1GHz as K is <1 to beyond 1GHz.

[G0HZU]

To give an example, if you look closely at the K plot for the MMBFJ310 when there is reactance at the gate it shows K is still below 1 up at about 1500MHz.

I put the s-parameter model into Genesys and designed a negative resistance oscillator at 1450MHz and the idea was to try and exploit the negative resistance generated up at this frequency by the MMBFJ310. See the genesys simulation where it shows there is still a net negative resistance even with lossy resonator components added to make up a 1440MHz oscillator.

I built the oscillator circuit on some copper PCB material and it oscillated at 1410MHz. Pretty close! See the spectrum analyser plot below. It probably is possible to get it to oscillate above 1500MHz but this must be close to the upper limit for the device. It does show how it is possible for these parts to oscillate up at UHF quite readily.

This oscillation at 1410MHz also helps to give confidence that I'm extracting valid s-parameter models (even up at UHF) for the MMBFJ310 using the VNA.

[G0HZU]

I managed to set up the VNA jig to allow me to extract a MMBFJ310 model in common gate at 12Vds and about 18-19mA Id.

I put two of these models in parallel in the Genesys simulator and the first thing of note was that I could only get a gm of 28,000umho compared to the 36,000umho obtained from the E430 in the article. See below for a plot of my simulation of the circuit in fig 4 of the HR magazine article.

This shows just under 7dB gain compared to just over 8dB for the E430 in a similar circuit in the HR magazine article. My result does look to be about right for 28,000umho and it includes a model for the 4:1 transformer with about 0.35-0.45dB loss across 30MHz to 200MHz. My model was of a transformer made from 5 bifilar turns 0.2mm enCu wire on a FT37-43 toroid.

My simple VNA derived models should be very accurate but they can't predict the noise figure or the large signal performance. I'd have to build the model for real to do that. There will also be a fair bit of variation in performance due to differences in Vp and Idss between samples of MMBFj310 and E430 devices.

My MMBFJ310 JFET that I measured on the VNA had Vp and Idss as below.
Vp = -3.58V
Idss 39mA

[A.Z.]

thank you ! you went a loong way, and sincerely, I didn't think that such an old article could raise so much interest, sounds like old tech is starting to be forgotten

As for gain, in own experience, the common gate setup won't give you much gain, but it will offer (at least on HF, where I played with it) good stability, nice impedance matching (for coax feeders) and decent IMD resilience, so in my opinion, it is a nice stage to have at the antenna input of a receiver, imagine having a wide passband filter (say 0.5 to 30 as an example) followed by a common gate whose output will go to a preselector, adjusting the common gate stage we could be able to compensate for signal loss caused by the filters and feed the following stage (probably an adjustable gain preamp) with almost the same signal seen at the antenna input

[G0HZU]

Thanks. It is a very well written article and I do have some interest in circuits like this because I did do a lot of design work with the J310 many years ago.

This evening I built the circuit in figure 4A but I didn't select/match the MMBFJ310 devices beforehand. I only managed to get 30mA Id so the gain was only 6dB. However the noise figure was 2.9dB at 30MHz and I suspect this would dip below 2.5dB (to agree with the HR magazine article) if I could cherry pick a couple of matched J310 devices with higher Idss. The gain would also improve as well.

[KE5FX]

See below for a VNA derived plot of K for a jellybean 2N3904 in common emitter configuration at 10Vce and 10mA Ic. The s-parameter data extracted from my VNA shows that self oscillation of the 2N3904 is possible at over 1GHz as K is <1 to beyond 1GHz.

These are nifty plots.  What generates them?  They're just based on the gain and phase of S21, nothing else?  I'm thinking I need another button on my VNA GPIB app.

[G0HZU]

See below for a VNA derived plot of K for a jellybean 2N3904 in common emitter configuration at 10Vce and 10mA Ic. The s-parameter data extracted from my VNA shows that self oscillation of the 2N3904 is possible at over 1GHz as K is <1 to beyond 1GHz.

These are nifty plots.  What generates them?  They're just based on the gain and phase of S21, nothing else?  I'm thinking I need another button on my VNA GPIB app.

They are generated using the last version of the old Eagleware Genesys RF simulator before it was sold to Agilent/Keysight in 2005. This old software allows some powerful post processing of full 2 port s-parameter data from a VNA. However, the plot below is just of resistance Rs looking into the resonator and the phase angle of zin1.

In this case I measured a 2N3904 at 10Vce and 10mA Ic in a VNA test fixture using bias tees and then imported the s11 s21 s12 s22 model into the simulator and used it in a negative resistance oscillator circuit. In this simulation I was scraping the last of the negative resistance the 2N3904 could generate at just over 1GHz. The VNA predicts the raw 2N3904 can actually generate negative resistance all the way up to 1200MHz at 10Vce 10mA Ic but this would require lossless resonator and feedback components in the oscillator.

See below for the negative resistance plot looking back into the resonator (at resonance) and the spectrum analyser plot of an actual 2N3904 oscillator built using the same circuit as the simulation. This kind of validates the s2p data from the VNA. It was a surprise that the 2N3904 could oscillate this high up in frequency! With today's fast BJTs I've used this technique for oscillator analysis all the way up to 16GHz with good results.

[G0HZU]

Here's the same VNA model data analysed and post processed in Genesys to show current gain for the 2N3904 at 10V 10mA. You can see in the right hand graph that Ft is predicted at 100MHz to be 314 because the 100MHz marker shows a current gain of just 3.14 at 100MHz. 100 x 3.14 = a predicted Ft of 314MHz.

The green trace on the graph on the left shows the classic 6dB/octave slope in current gain and it does cross zero at about 300MHz and this matches the Fairchild datasheet value for Ft quite well at 10Vce and 10mA.

[T3sl4co1l]

What's the configuration look like, for the 1GHz oscillator?

Tim

[G0HZU]

The oscillator doesn't really have a classic description as such. If you look back at reply #20 the K curve for the 2N3904 dips below 1 to just past 1GHz. Because this is a leaded part (non-SMD) there will inevitably be a few nH of inductance in each leg of the transistor. This is partly what makes it prone to instability.

All I did to complete the oscillator was to plot the instability circles in Genesys at 1GHz. Where the circles cross into the smith chart tells me what capacitive or inductive reactance to put at the collector and the base to make the system unstable at 1GHz. All I had to do then was crudely bias the BJT at 10Vce and 10mA Ic and then add the required reactances at the collector and the base legs. Then power it up and sniff the circuit with a small E field probe and a spectrum analyser to see it oscillating at just over 1GHz.

I used the same procedure for the 1500MHz MMBFJ310 oscillator. The main goal in both cases was to explore the highest frequency that the VNA data suggested the device could go unstable (at that bias point). I think If I used lower ESR parts for the reactances I could have got closer to 1200MHz for the 2N3904 oscillator and maybe 1600MHz for the JFET oscillator. It is very rewarding to see the circuit oscillate exactly where the VNA predicts it will and it does help prove that my VNA setup can produce decent s2p models up above 1GHz.

[David Hess]

The green trace on the graph on the left shows the classic 6dB/octave slope in current gain and it does cross zero at about 300MHz and this matches the Fairchild datasheet value for Ft quite well at 10Vce and 10mA.

There is or was enough variation in 2N3904 Ft that Tektronix used to grade them from a specific vendor for high Ft in some applications.

[G0HZU]

Yes, there's bound to be some spread in performance even within the same batch of transistors. I used a 2N3904 that I purchased from Farnell here in the UK. See below for the bag and Farnell part number. If I tested all 100 devices in the bag there would be some variation in performance in extreme tests like this.

I wouldn't recommend experimenting with 2N3904 devices purchased on ebay or from small time vendors as there is a huge risk that the part is fake or is something else rebadged as a 2N3904.

I think what is more relevant to this thread is that there will be a significant spread in performance for J310 JFETs. I picked out a MMBFJ310 part (also purchased from Farnell) that produced the expected 12mmho gm at 10Vds and 10mA Id to match the datasheet. Within that bag of 100 JFETs there will probably be a few devices that can produce sufficient gm to get close to the performance shown in the HR magazine.

I might have a go at making the version with the 9:1 transformer and a pair of MMBFJ310 JFETs in parallel. Even if I only end up getting 10dB gain it would still be an interesting amplifier design to play with.

[G0HZU]

I had a rummage in my s2p library of old autotransformer models and found an s2p file of a basic 9:1 autotransformer wound on a 61 material toroid. This was not a great transformer when it was tested as you can see in the second plot below.

However, I tried simulating it along with a pair of MMBFJ310 JFETs in parallel. The performance was much better than I was expecting. It managed just over 10dB gain up to almost 75MHz and the results were close to that of the HR magazine for the amplifier in figure 5 of the magazine article.
Note that I did struggle a bit with the 1.4uH inductor. Up at 75MHz the behaviour of this inductor will depend on the way it is designed and wound and also on its Q up at 75MHz. I found I had to put a 4k7 damping resistor across the inductor model to prevent excessive peaking up at 75MHz.

See the simulation plots below. Of all the amplifiers I've looked at so far this one is the most interesting. I think it deserves a better transformer than the autotransformer model I used in the simulation. This autotransformer was not wound the same way as the 9:1 transformer in figure 5 of the HR magazine. I didn't use three twisted wires. I just used a classic tapped autotransformer with 1 main winding wire tapped a third of the way along.

[David Hess]

Yes, there's bound to be some spread in performance even within the same batch of transistors. I used a 2N3904 that I purchased from Farnell here in the UK. See below for the bag and Farnell part number. If I tested all 100 devices in the bag there would be some variation in performance in extreme tests like this.

Just checked it again and they were grading 2N3906s for rb'Cc < 50 picoseconds which is an Ft of 600 MHz seems awfully far from the 2N3906's specified 250 MHz.  I guess rb'Cc is base transit time?

[G0HZU]

I've not tested many PNP BJTs like the 2N3906 so I can't really comment other than to ask what operating point are they testing at?

I can see a significant variation in Ft for the same BJT in the same test fixture when tested at a lower operating point. See below for the very same 2N3904 tested at just 0.5mA and 3Vce. The Ft drops from 300MHz to just 133MHz.

I usually measure s-parameters for a BJT or JFET across 3V, 5V, 7V, 10V, 12V and 15V and sometimes 20V. I also do this across 500uA, 1mA, 2mA, 3mA, 5mA ,10mA and 15mA for each voltage. Usually I do a log sweep across 300kHz to 2GHz. It's important to turn the VNA source power really low to prevent compression problems. I also use a carefully corrected test fixture that sets the reference plane very accurately at the device pins. I use the built in 'fixture simulator' feature in a 4 port E5071 VNA for this and I use a N4431B 4 port Ecal to calibrate everything.

https://www.keysight.com/gb/en/product/N4431B/rf-electronic-calibration-module-ecal-9-khz-13-5-ghz-4-port.html

I can try and create a classic VCCS transistor model to try and 'fit' the s-parameter data but I'd have to guess Rbb and see if it fits the s-parameter data at a chosen operating point.

[David Hess]

I've not tested many PNP BJTs like the 2N3906 so I can't really comment other than to ask what operating point are they testing at?

The test had to have been at 20 volts and 10 milliamps because that is what the Ft (min) was specified at, and the real circuits operated at that kind of current.  They gave the grading criteria but no details on exactly what the test was.

I can probably find the exact circuit the transistors were used in if you think it would be helpful; I think it was a 100 MHz PNP cascode so common base which is why I mentioned it here.

I can see a significant variation in Ft for the same BJT in the same test fixture when tested at a lower operating point. See below for the very same 2N3904 tested at just 0.5mA and 3Vce. The Ft drops from 300MHz to just 133MHz.

I usually measure s-parameters for a BJT or JFET across 3V, 5V, 7V, 10V, 12V and 15V and sometimes 20V. I also do this across 500uA, 1mA, 2mA, 3mA, 5mA ,10mA and 15mA for each voltage. Usually I do a log sweep across 300kHz to 2GHz. It's important to turn the VNA source power really low to prevent compression problems. I also use a carefully corrected test fixture that sets the reference plane very accurately at the device pins. I use the built in 'fixture simulator' feature in a 4 port E5071 VNA for this and I use a N4431B 4 port Ecal to calibrate everything.

https://www.keysight.com/gb/en/product/N4431B/rf-electronic-calibration-module-ecal-9-khz-13-5-ghz-4-port.html

I can try and create a classic VCCS transistor model to try and 'fit' the s-parameter data but I'd have to guess Rbb and see if it fits the s-parameter data at a chosen operating point.

There is an additional notation of NF being 6dB which made me wonder if Tektronix measured the noise figure to get an estimate of the Rbb (1), but the 250 MHz 2N3906 is marked as a 4dB noise figure which is the opposite of what I would expect, so I do not think they were measuring noise figure to calculate Rbb to get to rb'Cc to get to Ft, and they listed rb'Cc as the grading criteria and not Ft.

(1) That is the kind of weird thing I would do, but only after verifying that there was a real correspondence between them.  I never found a useful explanation about how to measure base transit time except estimating from Ft.

[KE5FX]

I had a rummage in my s2p library of old autotransformer models and found an s2p file of a basic 9:1 autotransformer wound on a 61 material toroid. This was not a great transformer when it was tested as you can see in the second plot below.

However, I tried simulating it along with a pair of MMBFJ310 JFETs in parallel. The performance was much better than I was expecting. It managed just over 10dB gain up to almost 75MHz and the results were close to that of the HR magazine for the amplifier in figure 5 of the magazine article.
Note that I did struggle a bit with the 1.4uH inductor. Up at 75MHz the behaviour of this inductor will depend on the way it is designed and wound and also on its Q up at 75MHz. I found I had to put a 4k7 damping resistor across the inductor model to prevent excessive peaking up at 75MHz.

See the simulation plots below. Of all the amplifiers I've looked at so far this one is the most interesting. I think it deserves a better transformer than the autotransformer model I used in the simulation. This autotransformer was not wound the same way as the 9:1 transformer in figure 5 of the HR magazine. I didn't use three twisted wires. I just used a classic tapped autotransformer with 1 main winding wire tapped a third of the way along.

The inductor can be dispensed with if you are interested in HF.  It has no effect on NF or anything else besides VHF gain (and I suppose S22.)

I tried the figure-5 amp just now with a CPH6904 (dual CPH3910) at its max Id of 40 mA in place of the E430.  It worked fine.  Best performance I saw was 12.7 dB of gain at 50 MHz with NF in the 1.5 dB range.  At currents less than 40 mA, the VHF gain fell off, the HF gain came up, and the NF was largely unaffected.  The input impedance varied quite a bit with Id. 

I didn't see any peaking, but I also didn't try any inductors other than the 910 nH / ADT9-1T combination in green.



Reverse isolation is more like 30 dB rather than 36 dB predicted by the article, but I didn't characterize it versus Id.  I also didn't check IP1dB but it was +6 dBm with a single CPH3910 configured for 10 dB of gain at 10 mA, so likely better now. 

Of course 40 mA at +/- 12V is almost a watt, so you wouldn't normally run the part this hard.  (Edit: there is also some saturation in the Mini-Circuits transformer at this current level, so AC-coupling the transformer buys another dB or so of gain.  NF is unaffected as is the oddly-poor LF performance.)




Good part.  Everybody buy lots of them, so they keep making them.

[biastee]

Yes, it's the introduction of some inductance at the gate connection that can lead to instability up at UHF.

The second plot shows K when just 4mm of leg inductance is added at the gate and this simulates what you might see from a non-SMD part. You can see that K goes below 1 over much of VHF and UHF. This opens the door to instability. This is just at 10mA Id. It would be a bit worse at 18mA ID and even worse again if two were placed in parallel. This should show that this type of amplifier is really prone to instability up at UHF unless care is take to ensure a short gate connection. If you use the T0 plastic J310 then you really do have to try to cut the gate leg 'really' short and even then I suspect it wont achieve a K over 1 at UHF. However it will help reduce the chance of instability.

I share G0HZU concern over common gate's sensitivity to ground inductance. In a 435 MHz amp, a dual gate mosfet (which is a cascode of CS & CG) BF988 / 998 developed an unintended gain peak at ~1.6 GHz (black trace in gain graph) when the gate 2's bypass capacitor (C4 in the attached photo) is located 5 mm away from the transistor package. Replacing C4 with a 0805 chip at ~1mm away, eliminated the gain peak (blue trace in gain graph).

However the noise figure was 2.9dB at 30MHz and I suspect this would dip below 2.5dB (to agree with the HR magazine article) if I could cherry pick a couple of matched J310 devices with higher Idss.

Noise matching the J310 at 98 MHz resulted in 0.4 dB NF whereas conjugate matching achieved 3 dB NF (attached image)

[G0HZU]

Some good results there from KE5FX and biastee! I'll have to check out the CPH6904 and CPH3910 JFETs on the VNA. They do seem to have a very high transconductance compared to the J310.

I don't think I've ever managed to get a NF below about 1.5dB with a U310/J310 at VHF but usually I aim for a compromise between input match and noise figure.

[G0HZU]

I had some free time today and managed to take a suite of s-parameters for the CPH3910 JFET at various operating points.

I haven't built any amplifiers but I did try to marry the s2p file up with various transformer models I have here.

One interesting result was with an S2p model of a 49:1 transformer with some compensation. The simulation predicts about 14dB gain across 1 to 14MHz with fairly good input and output match across this range. This was with a pair of CPH3910 JFETs in parallel each biased at 10V and 15mA.

I'm not sure what practical application this amp has but it was interesting to see the result. The gate inductance needs to be sub 1nH to maintain K above 1 up at UHF with this simulation.

[G0HZU]

Based on my s-parameter measurements here's a plot of GMAX and K for a single CPH3910 at 10Vds and 15mA. You can see that K dips below 1 even with a directly grounded gate pin. If the inductance of the gate connection goes up to just 1nH see the second plot for what happens to K up at UHF. I think great care is needed with this device to manage stability. It looks like this device can oscillate up above 2GHz.

[Gerhard_dk4xp]

Now that you have measured the s-parameters, would you share them?
It would remove the need for me to do that over the holidays.

I found that an array of 16 ON CPH3910 oscillates happily at 650 MHz,
working common source into a bipolar cascode. And every gate has a
different AC voltage, even though they are connected by relatively short
traces; 2.4 GHz scope including active probe
(16 pcs. in par for voltage noise reasons)
The parallel lines are an efficient  coupler. It took a ferrite bead in each
gate and a 0603 cap at each drain to kill that. ~2nF in total until it began
to impair my 2 MHz baseband bandwidth. (cascode is low impedance)
I admit it could take less, but I was fed up with oscillations.

BTW NSVJ3910 is quite repeatable. Cannot be compared to IF3601 etc.

[G0HZU]

Hi Gerhard
I only have CPH3910 s-parameters in common gate so far. If you let me know the operating point of your CHP3910 in common source I can measure a set of  s-parameters for you. Note that my test setup only supports up to about 15mA current. I should be able to do up to 20V at 12mA or maybe 15V 15mA but that is about the limit. I do measure the dc operating point very accurately, usually to <0.5% using a pair of DMMs. What is the BJT you use in the cascode and what is the dc operating point?

[Gerhard_dk4xp]

45 mA/ 3V for 16 FETs. The Cascode is folded, with BC860.
I will probably unfold it since I need more than 2+2 Li batteries anyway.
Bandwidth is only 1Hz to 2 MHz but the 3910  is much faster.

Don't measure it when you don't need it yourself. My ZVB8 has built-in
bias-tees, so it is no effort with the test circuit.

73, Gerhard

[G0HZU]

OK thanks. 45mA is way too much for my test fixture so probably best you measure it with the ZVB8.

I had a go at doing a practical LNA design using the CPH3910 s-parameters today. The aim was to make a low noise preamp for the 88-108MHz band. See below for the simulation based on the s-parameters at 10Vds and 10mA. The result was quite good in terms of passband gain and port match across 88-108MHz. I'd expect it to achieve a noise figure of about 3dB but with an L match at the input this could probably achieve 2dB noise figure with a bit of input mismatch.

I'd expect the OIP3 to be better than +20dBm so this would be a cheap LNA for the 88-108MHz FM band with 13dB gain and fairly good noise and signal handling performance from just 10mA.

[G0HZU]

I just built the VHF FM LNA circuit this evening but I tweaked it for 50 ohm ports rather than the expected 75 ohm. This makes it easier for me to measure as all my test gear here has 50 ohm ports.

See below for the simulation (based on my s-parameter data of the CPH3910 and some simple circuit models for the R, L and C components) and this is compared to a measurement of the built circuit using the VNA. I think if I had measured the inductors on the VNA and I had modelled the circuit strays better in the simulation the agreement would have been closer. Even so, there will be some spread due to component tolerances.

This does at least show that I can measure s-parameters of SMD components quite well!

I'll have a go at measuring the noise figure and the signal handling tomorrow.

[KE5FX]

Nice.  That's a tight match!

[Gerhard_dk4xp]

The 45 mA is for 16 transistors, not for one. In a single FET, the voltage
noise improves only with the 4th root of drain current, so there is no point
to overdo this.

The measurement of Id over Vgs was really to make sure that the 3910 are
close enough to put them simply in parallel. The Interfet IF3601 stray so much
that with a given Vg some may be fully open while others still are closed.
The closed ones would add capacitance while doing no contribution to
voltage noise performance.

For the 3910, it is OK.

I'd like to see if I can extract the parasitics of my layout with ElectroMagnetics 
to predict the instability. Probably a non-starter, for me being just a beginner
with that.


The common gate JFETS with Zin= 50 Ohms remind me of the ring mixer
terminations proposed by DJ7VY and Ulrich Rohde some 35 years ago.

[G0HZU]

Hi Gerhard, if you can confirm that the Id is 45/16 = 2.8125mA and the Vds is 3V (as in the dc voltage measured across the drain and source rather than just the voltage of a 3V power supply) then I can have a go at measuring the s-parameters in common source. My CPH3910 devices are made by On Semi and purchased at Farnell so should be genuine parts.

Nice.  That's a tight match!

Thanks! I'm lucky to have some nice test gear here so I'll try and measure the noise figure tomorrow. My noise figure setup is about as good as it gets for hot/cold Y factor hardware and I think the overall uncertainty is very low. I think the noise figure will be a bit worse when tested at 50R. I'll also try measuring the NF with a simple L match to step up the source to 75R. I'm expecting to see about a 2dB noise figure with the L match.

I did quickly measure the OIP3 and it was a fairly consistent +20dBm across the whole band. Increasing the supply voltage slightly improved it to just over +20dBm.

[coppercone2]

I would have said that a 2 to 3 dB noise figure is pretty good for a commonly available part and simple circuit, but at HF and maybe 6 meters, that is more than enough performance because of high levels of background noise.

I would like to see more about how to produce high IP3 and compression for an low noise LNA, but the measured performance is pretty good, although power consumption is high as well.  The designs I remember use a differential two transistor common-base amplifier.

A lot can be learned from old articles like this.

I keep hearing about HF and background noise (run into a limit), but what happens to lunar or spaced based HF transmitters?

I thought maybe there is a good reason to investigate this for hobbyists interested in some kind of cubesat etc.

[ProphetM]

I just built the VHF FM LNA circuit this evening but I tweaked it for 50 ohm ports rather than the expected 75 ohm. This makes it easier for me to measure as all my test gear here has 50 ohm ports.

See below for the simulation (based on my s-parameter data of the CPH3910 and some simple circuit models for the R, L and C components) and this is compared to a measurement of the built circuit using the VNA. I think if I had measured the inductors on the VNA and I had modelled the circuit strays better in the simulation the agreement would have been closer. Even so, there will be some spread due to component tolerances.

This does at least show that I can measure s-parameters of SMD components quite well!

I'll have a go at measuring the noise figure and the signal handling tomorrow.

Hi G0HZU,

Please do you still have the schematic for this amplifier?
I've tried designing a "wideband" amplifier from s-parameters with no luck.

Maybe the solution is to do wideband matching : more than 2 reactive elements ?


Thanks

[LM21]

Interesting. It is nice to build using basic components, but do you know that there are low noise MW ICs with large frequency range.

I once had a nice analog FM tuner/receiver made with RCA 40822 dual gate mosfets. It had a low noise figure and fets were soft(easily overloaded) that I could hear many narrow band FM transmitters (Taxis), and  aircraft AM with it. So I  am not very quick to trust fets as LNAs.