Stacking FETs in RF circuits

[ezalys]

I’m working on a circuit that is currently limited by the Vds of the involved FETs. It would be super helpful to get another effective factor of 2 or 4 on that figure. Is it reasonable to stack FETs in series in RF circuits (up to 1.5 GHz) or is that a no-go? Is the only alternative to use expensive GaN HEMTs?

[T3sl4co1l]

You certainly can, but is it still going to look "in series" when common mode is included?

Model it.

Tim

[rfeecs]

AMCOM does it with GaAs FETs:

https://www.amcomusa.com/documents/publications/June2011a.pdf

They are probably more expensive than some GaN devices.

Also, the combining is all on one die, so minimal parasitics in between the devices.  Even dual gate (cascode) GaAs FETs can be tricky to keep from oscillating.

[David Hess]

For discrete low and medium power devices, I have only seen it done up to 100 MHz.

[TheUnnamedNewbie]

Stacking has been done for this exact reason on-chip for a long time now (getting good output power with 1V Vdsmax is not exactly easy). I have seen it done up to 70 GHz (on CMOS) I think.

[David Hess]

Stacking has been done for this exact reason on-chip for a long time now (getting good output power with 1V Vdsmax is not exactly easy). I have seen it done up to 70 GHz (on CMOS) I think.

I have seen cascode and distributed but stacked?

[JohnG]

Is it RF in the more traditional sense of a modulated carrier, or is it generating a particular waveform with a lot of RF content, e.g. fast edges? If the former, why not use a transformer and/or power combiner to get the voltage you need? I'm asking because I don't know any details of your circuit, especially what voltage you are after. Is 1.5 GHz your cutoff frequency, or do you have higher frequency harmonics that you care about?

Stacking devices is difficult in practice, and it gets more difficult the faster you have to switch. It adds a lot of inductance, you have a lot of floating switch drivers, you have to get the timing right, and you have to think about device matching and/or additional circuitry to deal with mismatching.

John

[TheUnnamedNewbie]

Stacking has been done for this exact reason on-chip for a long time now (getting good output power with 1V Vdsmax is not exactly easy). I have seen it done up to 70 GHz (on CMOS) I think.

I have seen cascode and distributed but stacked?

Hmm, perhaps I misunderstood what the OP meant with stacked. How else are you going to stack devices if not cascode?


EDIT: I should read before posting, only now checked publication referenced early.
I have not seen anyone do that at 70 GHz

[David Hess]

Stacking has been done for this exact reason on-chip for a long time now (getting good output power with 1V Vdsmax is not exactly easy). I have seen it done up to 70 GHz (on CMOS) I think.

I have seen cascode and distributed but stacked?

Hmm, perhaps I misunderstood what the OP meant with stacked. How else are you going to stack devices if not cascode?

A cascode has many benefits but does not actually increase peak-to-peak voltage which is still limited by the cascode transistor.  Stacking, at least the way I was thinking of it, means driving the base of the "cascode" transistor so that the collector voltage of the lower transistors is a fraction of the output voltage so the collector voltages of the output transistors add together.  The transistors are both driven and in series.  This configuration is used in high power audio amplifiers and some wide bandwidth baseband amplifiers like for oscilloscopes where a higher voltage RF transistor was not available.

[ezalys]

1.5 GHz is a sort of cut-off, and I need to generate a very sharp pulse with absolutely minimal ringing. The FETs are there partly to just drive into saturation to sharpen the pulse.

[JohnG]

Without some actual detail on the waveform and system, it's pretty near impossible to provide any insight. We don't know the load, the interconnect, what ever "very sharp" means, etc. Ringing will depend on the whole circuit, not just the FETs. There are all kinds of things that can ring, and they can all be excited by a "very sharp" edge.

But, it is likely that adding multiple FETs in series is going to add considerable inductance to the circuit, and this will most likely make ringing worse. Multiple FETs take more physical space, and worse, they are connected in series, which means the physical layout will tend to be longer and thinner. This will increase inductance.

How much inductance matters? That depends on the rest of the system. The higher the current, the more the inductance will matter. If you are switching 10A/ns, you will get a 10V spike for every nH. If it shows up primarily at your FET drain, maybe it's ok. If it shows up primarily between source and gate, you will be in trouble.

A rule of thumb for a bond wire in free air is about 1 nH/mm. This is worst case, typically.

If my numbers are not close to anything you are doing, that's because I have no idea what you are doing .

Also, it would really help to know what voltage you are trying to get to. If it's under 200V, GaN devices are not that expensive (disclaimer: I work for a GaN device manufacturer). They get pricier above 200V, but it might still be cheaper in the long run. Although, I would be remiss if I did not mention that you can also get some crazy fast voltage rise turn-off edges with superjunction MOSFETs due to circuit inductance because their output capacitance is so non-linear.

Cheers,
John

[ezalys]

I'm switching 20 volts at 500 mA, and the transition should be around a nanosecond for the 20%/80% time.

[ezalys]

I may just order some EPC8002s and CGHV27015S'es and make some dev boards and have some fun.

[rfeecs]

I may just order some EPC8002s and CGHV27015S'es and make some dev boards and have some fun.

I'm sure you know these are two different animals:
EPC8002 is Enhancement mode GaN on Si.
CGHV27015S is Depletion mode GaN on SiC.  About 10x more expensive.

[ezalys]

Well, I'll say that the 10x price is not such a big deal for my application. The performance in circuit is the most important thing. Also, the circuit can be trivially modified for negative Vgs. I'm really not sure how to compare the two devices for my application. Ultimately we try to saturate a collection of FETs to generate a very pure square edge with minimal ringing and require the 20 volts Vds at 500 mA Ids, and nanosecond 20%/80% time. Obviously this will depend largely upon the circuit which I can't share...

I really have no experience with these GaN devices. I mostly have experience playing with little dollar broadcom HEMTs in low power high speed stuff.