Many thanks for the replies. I can ask more questions now
As always, the question is: how flat do you need?
I have a toy project to study and/or practice different topics, a pulse generator. At the moment I am at 500ps rise time, I would like to push this up to 100ps at least. So if I am correct, I am looking into 1Ghz, then up to 5Ghz bandwidths.
You can always relieve ground underneath the pin/pad. How much (to layer 3 or 4?), by how far (clearance), and how to taper from low to high microstrip (some kind of taper), all fine questions best answered with simulations or protos, but just a basic effort should at least extend it say an octave or two (so, many GHz).
Let me repeat what you say to see if I understand it correct. Because the center pin/pad is larger than the trace, and if that cannot be changed, I can change the distance to keep the impedance same. So normally I have traces on top, the reference copper plane at layer 2, and copper plane also at layer 4 just because of the connector. So, for example, if I look at the cinch's table for 1.6mm board, I can make an empty area in the copper plane at layer 2 at (or close) the connector pads, and then use the copper at layer 4 for the microstrip of the center pin/pad. Did I understand this correct ? and just by doing this if it works up to 10 Ghz or so, that is very OK.
I just started looking into simulations, sonnet lite at the moment. Happy to hear if you have any recommendations on this, as I am a bit confused, I think not many software are free, and traditional FEMs seem to me a bit complicated to use only for this purpose.
You can fairly easily figure out how big a deal this is, the pad is just a bit of extra shunt capacitance. You can calculate how big it is and see what the effect is. If the excess capacitance is not too great you can deliberately add some series inductance to impedance match to 50 ohm. That effectively turns it into a lowpass filter with (hopefully) the cutoff frequency well above your band of interest. If you are using this in the ~1 GHz region where FR4 is normally considered suitable, chances are that the effect is small and can be corrected in this way.
I have built a prototype and it is OK up to ~500ps rise time, and then I wanted to move this into PCB. My first try was >1ns, I realized I forgot something but meanwhile I realized this SMA connection issue (I had pigtail SMA not a connector on the prototype) so I want to have my second try addressing it as well, hence this question.
I have an oldish TDR meter (CSA803C), I can see (I think) at the pad it decreases to ~16ohm (the blue dip in the attached photo). What do you mean exactly to add series inductance to this ?
You can remove the middle ground planes near the connector. Effectively launch to a microstrip between the top and bottom layer, then transition to the desired waveguide with a properly engineered transition. If you have a good RF board (i.e., not a cheap JLCPCB prototype) you can do pretty well with this, especially if you are willing to characterize the process carefully and iterate the design.
OK, I think then I understood what Tim and you said correct (which I repeated above). I am not planning to use any special material for the board, since this is just a toy project, and until I understand all the issues, but I dont know what I am saying as I dont know the limit of FR4. If 100ps/5Ghz is not doable with "normal" FR4, I would love to hear this.
One cute trick is to try to keep the ground currents from having to hop planes. For instance, if you cut away the plane on layer 2 near the connector you have a microstrip between layers 1 and 3. On a normal PCB you will still be able to have a reasonable geometry in this configuration although you have to work to make sure that the connector ground properly contacts layer 3. Then you use a via from layer 1-4 to transition to a much smaller bottom layer microstrip still referenced to layer 3. Since the ground current doesn't have to hop planes (technically it moves from the top side to bottom side of the same copper) you get a compact and high performance transition.
Normally I just keep layer 2 (for the traces) and bottom layer full copper (for the connectors, no particular reason I make it a plane). So what you (and Tim) describe:
- I keep layer 2 as copper plane for traces, but make an empty region at the connector to have pad/center pin referenced to another layer (lets say to bottom layer).
- I dont use layer 3, so I just keep it empty=no copper ?
- I keep layer 4 as copper plane or just a copper region around the connector ? I have layer 1-4 vias at connector and other places connecting layer 2 and layer 4. Do I need more connections/more vias between layer 2 and layer 4 ?