Testing the effects of releaving ground plane beneth a component

[joeqsmith]

This experiment is just for the fun of it.  For some background, see the following thread:
https://www.eevblog.com/forum/rf-microwave/can-a-siggensadirectional-coupler-be-used-as-a-poor-mans-scalar-analyzer/msg3605548/#msg3605548

A few takeaway points from this thread are:

I'd like to test the level of impedance mismatch caused by component footprints on PCB microstrip layouts, up to 3 GHz.

... I already did some simulations and the results even looked real ....

... motivation is to get a reality check - can I trust my simulation setup?

A 0603 AC coupling capacitor footprint between a 50-ohm microstrip, far-end terminated by a 50-ohm coax load, One has solid ground plane and another has cut out.

My intent:

I had made up a test board using some ATC (prior to the AVX debacle) 100B RF jelly been parts.  Three caps were mounted to a test board configured as a shunt thru, series and shunt.  I could mount a fourth capacitor to the same type PCB, series configuration, using the same connectors.  We could then compare the return loss for the two PCBs.  It's not much of a test but may give you some confidence in the variance.   I could then remove  2mm sq from the ground beneath the cap and remeasure it.    I could provide you with details about the build that you could then attempt to simulate and see how the results compare. 

I would also like to use both the original NanoVNA and along with the V2Plus4 to collect this data.   The OP wasn't forthcoming with details about their particular simulation but if anyone has access to ADS, HyperLynx or other simulators and want's to donate some time, that would be very helpful.  My plan would be to provide enough detail to allow you to create a model of the hardware (assuming I am able to detect any changes).  Again, the goal is to see if the simulation give even a rough result of the actual hardware.     

To give this test any sort of meaningful result, if that were at all possible, the first thing I plan to do is make a new set up standards and characterize them against a known set rather than using the ideal model.     

Any feedback on this experiment is certainly welcome.   

[joeqsmith]

Recently I had posted a demonstration of my software for these low cost VNAs.    Part of this was measuring a capacitors ESR.   To make these measurements, I had mounted a few parts from American Technical Ceramics to a coplanar waveguide that I plan to use as a control for this experiment.   The parts I used area a 100B331JP 200X, 330pF 200V 5%.   These particular parts were produced prior to AVX taking them over.     



A second board will be assembled using a component from the same lot.  The same connectors and series coplanar waveguide will be used.  We will start by measuring the differences between two boards.   Assuming there is little difference, we will then relieve the area beneath the capacitor and remeasure the board.   Seems simple enough. 
 

[joeqsmith]

Shown are the new calibration standards along with a second test board with the ATC device mounted to it.

The range will be limited to 1.5GHz.  This is the upper limit of the original NanoVNA.  The test boards behave poorly as we move beyond this.   

I plan to use the Short and Open from the PCB standards but will use one of the sorted Mini-Circuits ANNE parts for the load to improve the return loss. 

A MidWest Microwave terminator will be used to terminate the unused port on our test boards.  This part was also sorted based on the return loss. 

[joeqsmith]

I wanted to get a feel for what sort of an difference we would see when removing material below the component as a sort of swag.  So a third board was populated with the same capacitor.   

For starts I inserted the test board several times, hand tightening the components.   I did this because so many internet experts have told me that hand tightening is every bit as good as using a torque wrench.   I then used my Dremel to cut a 1mm slit below the component and made one last sweep. 

[joeqsmith]

Several people wrote about their horror stories of damaging connectors with a torque wrench.   A common theme was how the connectors on the NanoVNA are poorly soldered and were easily damaged. 

I set out to do some destructive tests on some edge mount connectors.  Some, fairly expensive, others bottom of the barrel.   Some where not even soldered to the board.  This video should give you some idea of just how much force it really takes to rip a connector from a board.   

[joeqsmith]

I then repeated the test, torquing the connections between each measurement.  A second slit was then cut into the board and one last measurement was taken (with it properly torqued). 

[joeqsmith]

Using an X-acto knife, I cut away roughly 3.5mm of material and remeasured the board.   

[joeqsmith]

Up to this point, all of the data has been taken with an old Agilent PNA.  Now that I have some idea what we are looking for,  lets try and look at our actual test boards using the low cost VNAs.   

I'm going to go out on a limb an say the original NanoVNA is not well suited to make this measurement.  Again, I don't recommend it for use over 300MHz.  You can see it's signal starts to diverge at around 150MHz.   But, it's $50.   The V2Plus4 on the other hand is tracking the PNA fairly well.  No surprise as I have compared these two instruments in other tests.

[joeqsmith]

Attached all three VNAs measuring both the mag and phase for PCB 2.   

[joeqsmith]

Looking at the datasheet for the ATC100B331J, they provide S-parameters from 50MHz to 4GHz.    They show a resonance at 1.1GHz, 2.1GHz and 3.1GHz.   AVX requires you to register to obtain the S-parameter data, so I have attached the Touchstone file.  You will need to rename it.   

PCB2 was swept  to 4GHz.  There is resonance at  670MHz.   This shows up on PCB1 as well.   A part was inserted into my test jig.  It does not have this resonance.    I did state in the original post:   

Again, it would be very crude.

   

I am really liking the METAS software for viewing the data. 

[joeqsmith]

Not surprised no takers on the simulation side.  I hate to think of the cost.  Keysight offers a 30 day trial for ADS but it may take me that long to learn the basics.      The design is so simple, I would expect if they offered some sort of student version, it may be able to simulate the design. 

https://www.keysight.com/us/en/assets/3120-1063/configuration-guides/PathWave-Advanced-Design-System-ADS-Configuration.pdf

Another option? 
http://dd6um.darc.de/QucsStudio/screenshots.html

[joeqsmith]

The free simulator seems easy enough to use so far but ran into a problem before I even got started.  Note that when using S-parameter data, the only packages supported are SOT23 and TO92.   Pushing ahead with the SOT23, it seems to somewhat work.   I am able to change the coplanar dimensions and it certainly effects the simulation.  PCB is next....

[joeqsmith]

Selecting the option to create the layout causes the attached error.   It's possible to create the netlist and load it in but I suspect to run the simulation it all needs to be tied together. 

I joined their forum.  Maybe someone their can help get it running. 

[joeqsmith]

Looks like the QucsStudio forum censors the posts, so no luck there.     

Attempting to manually create the PCB layout, many of the library components are not supported,  which includes coplanar.   I created a new schematic using microstrips which are supported.  If I add a capacitor (you have to use the lumped model)  and wire it across a microstrip gap, the software will not include it when creating the layout.  You can however add the capacitor to the layout directly. 

The simulation starts without any errors and made it to 87% complete where it has been for about an hour now. 

Even if it would run, the software is lacking the ability to use S-parameters capacitors.  The next problem I see is that I am unable to find a way to modify the ground plane. 

[joeqsmith]

Removing the capacitor, so there is now nothing beyond a gap, the simulation will run.  Shown with a whole 4 data points (attempting to speed things up). 

Manually adding a lumped capacitor back in, the simulation will again run.   It appears not to like it when I set the range to DC min.  I suspect this is the problem I was running into before when using the cap.   If I set it to free, it throws a warning about starting at 50MHz.  Starting at 100MHz avoids this warning but without the proper model, S21 is not close to correct.   The layout does not appear to support the S-parameter model or I would try and use the SOT23 for the capacitor and add it.   

[joeqsmith]

I spent some time looking for other EM solvers but no luck.  Attached are the QucsStudio and AppCad settings along with the S-parameters for the capacitor and package size. 

I have posted a comment to Robert Feranec to see if he would be willing to help out.    He has made several top notch videos using the ADS simulator.   Check out his channel.
https://www.youtube.com/channel/UCJQkHVpk3A8bgDmPlJlOJOA

[rf-messkopf]

Looks like the QucsStudio forum censors the posts, so no luck there.

Looking at the forum homepage the last post in the "Usage" section was by user JOEQSMITH 2 weeks and 2 days ago, which cannot be correct, and your posting is not displayed when I open that section. To me this looks like a technical error. Have you tried contacting Michael Margraf?

Attempting to manually create the PCB layout, many of the library components are not supported,  which includes coplanar.   I created a new schematic using microstrips which are supported.  If I add a capacitor (you have to use the lumped model)  and wire it across a microstrip gap, the software will not include it when creating the layout.  You can however add the capacitor to the layout directly. 

Including a capacitor works for me, with and without including a microstrip gap, which I believe is not necessary for the EM-simulation. As for coplanar waveguides, I think they are currently not supported in the EM solvers layout creation tool. But you can run a regular S-parameter simulation with the built-in coplanar waveguide models, together with lumped components. This may or may not be a good approximation to a real EM-simulation. For these conventional S-parameter simulations you can also include S-parameter files.

The simulation starts without any errors and made it to 87% complete where it has been for about an hour now. 

I'm by far no expert when it comes to EM-simulations, but you can try to modify the simulation parameters when the simulator hangs (under File -> Document Settings). In the "File Properties" dialog box there is a tab "Excitation". Set "Energy Decay at End" to a larger value, as this determines the termination condition of the simulation. You can also try to modify the mesh size under "Domain". And you can always hit the "Terninate iteration" button and get the result from the current iteration.

Even if it would run, the software is lacking the ability to use S-parameters capacitors.  The next problem I see is that I am unable to find a way to modify the ground plane.

As I already said, I believe S-parameter files are only usable with regular S-parameter simulations. I have no idea how to modify the ground plane or if that is even possible from within the layout editor. Maybe only if the layout data is created externally and then imported? The underlying solver is 3D, if I'm not mistaken, so it should be able to do that. I have never used qucsstudio for such complex simulations though, only for simple microstrip filters.

Or one could try to use openEMS directly: https://openems.de/start/. Again, no expert here, and I have never done that, and there is nu GUI.

I really would like to take a deeper look into the capabilities of qucsstudio, but I have virtually no time during the coming days.

[joeqsmith]

I have not tied to contact the forum about my post from last night.  I joined and posted within a few minutes.

As I already said, I believe S-parameter files are only usable with regular S-parameter simulations. I have no idea how to modify the ground plane or if that is even possible from within the layout editor. Maybe only if the layout data is created externally and then imported? The underlying solver is 3D, if I'm not mistaken, so it should be able to do that. I have never used qucsstudio for such complex simulations though, only for simple microstrip filters.

It sure seems like this is correct. I have not tried to import the layout and assumed it all had to work together.  Without the EM solver having support for S-parameters, I saw no reason to continue.    Too bad as the software seems fairly user friendly.   

****
I suspect that the 2weeks 2days you mention is the last time that area was posted to.   Because they have not allowed my question to be posted, it had not updated the time.   See attached. 

[G0HZU]

One thing to watch out for is that the ATC s-parameter models are taken over a PCB substrate so I'm not sure it is a good idea to use them anyway. These capacitors behave differently when mounted vertically or horizontally and this is because the metal structure within the cap body acts a bit like a transmission line when mounted over a given substrate. This is part of the reason these caps have sharp resonances and they often aren't suitable for wideband design work.
 
For your EM simulations you can try playing with (free) Sonnet Lite but I think it only allows a perfect capacitor model in the Lite version. It probably will let you play with the groundplane but I've not really used the Lite version very much.

One thing worth noting is that it can sometimes be a good idea to deliberately use fatter pads (compared to the ideal microstrip width) for the component if it has a tiny amount of series inductance. The fatter pads and the series inductance form a pi network and this can help improve the s11 response up at UHF.

At work I use Genesys and Sonnet combined together for stuff like this. I've used various EM simulators and Sonnet always comes out top for the most critical tasks. It can do multi layer simulation and can allow custom groundplane shapes with gaps. When used with Genesys it allows s-parameter models allowing very good simulation of LNAs and lumped+ distributed filters. It is a very powerful combination in my opinion.

I'm not really sure what you are trying to do but I suspect there will be cases where removing part of the groundplane will actually make things worse and sometimes it will help. A lot depends on the component and the pad shape it requires. Also, a lot depends on the chosen PCB material in terms of dielectric constant and substrate thickness.

[joeqsmith]

From the OP:

... motivation is to get a reality check - can I trust my simulation setup? 

A 0603 AC coupling capacitor footprint between a 50-ohm microstrip, far-end terminated by a 50-ohm coax load, One has solid ground plane and another has cut out.

My interest was to see if I put together a simple circuit and made the change they suggested, would a simulation show a similar change (good bad or otherwise).   

It sounds like you are setup to run this little experiment and have your own ideas on how it should be conducted.  Feel free to join the fun. 

[G0HZU]

If it helps I just re-read the thread and I'm not sure what is happening between the plots test1 and test2 shown below. Test1 does look like the response for a 330pF cap but I'm not sure what has happened for test2. If I read the thread correctly this is supposed to be the better measurement because you used a torque spanner.

It no longer looks like a 330pF cap so I'm not sure what is happening here. Have you damaged something in the test setup? Is there an intermittent connection somewhere? I assume the odd trace is the one you took after the second slot cut. Again, I'm lost as to why you would see this degree of response change down at 50MHz. Can you explain test2 for me because it looks to me like something went wrong with the return loss response across 0-500MHz.  However, nobody else has spotted an issue here (including you) so I'm left confused as to what test2 is actually proving. What have I missed here?

[joeqsmith]

If it helps I just re-read the thread and I'm not sure what is happening between the plots test1 and test2 shown below.

I would say it helps. 

Test1 does look like the response for a 330pF cap but I'm not sure what has happened for test2. If I read the thread correctly this is supposed to be the better measurement because you used a torque spanner.

It depends on the perspective.  Test one was a hand tighten only causing a wide spread setup to setup.   No surprise.  Effect of cutting the board could still be detected.   Decided to repeat the test but doubt I took the time to load the cal.   I was just wanting to show how it would tighten up the measurements.   In both tests, I was getting an idea of how much change to expect and if the low cost VNAs would even be able to detect it. 

It no longer looks like a 330pF cap so I'm not sure what is happening here. Have you damaged something in the test setup? Is there an intermittent connection somewhere? I assume the odd trace is the one you took after the second slot cut. Again, I'm lost as to why you would see this degree of response change down at 50MHz. Can you expline test2 for me because it looks to me like something went wrong with the return loss response across 0-500MHz.  However, nobody else has spotted an issue here (including you) so I'm left confused as to what test2 is actually proving. What have I missed here?

Often you will find I won't take the time to calibrate the system if I am just looking for general trends in the data.  In this case, I doubt I reloaded the previous cal.  I'm guessing that's not how you are used to working.   For me, calibration is commonly the last step.  It takes time, wear and tear on the standards and may not need that level to get the basics sorted out.   Eventually, if I run the test, I will take the time to do a proper setup.   

[G0HZU]

Thanks, but regardless of the obvious s11 cal error in test2 ​take another look at your test2 plot traces that you connected up with a torque spanner. At about 20MHz you are seeing a 2dB variation in return loss each time you reconnect up the system. You seem to conclude that you have proved how good a torque spanner is compared to using fingers because this seems generally more consistent in places compared to test1.

However, at 20MHz with a DUT return loss of maybe 12-13dB even a toddler with tiny fingers could achieve remarkably repeatable results assuming the test fixture and cables are solid. Even with toddler finger torque I'd expect to see <0.1dB difference between S11 traces at 20MHz. But you have managed 2dB variation using a torque spanner...

Something is clearly wrong with your setup. Are you using cheap and nasty ebay SMA connectors with crazy tolerances? Is your PCB and/or the 330pF MLCC intermittent/cracked somewhere? Do you have a faulty cable somewhere? This might also explain why the return loss profile is so obviously wrong for a 330pF cap in test2.

[joeqsmith]

That's very true.   I could repeat the test easy enough.  The srcap board is still sitting here, with a very large hold in it. 
***
Board and terminator appear fine.   

[G0HZU]

I think it's definitely worth checking everything over carefully. In my time at work I have tinkered with countless RF dev boards and often there comes a time where repeated handling of the board finally takes its toll on something. Often a MLCC cap will crack or a connection to an SMA end launch connector will develop a microscopic solder crack or maybe an RF cable can lose some quality in its end connections. Once any of this happens the whole test system isn't your friend anymore.

[joeqsmith]

Question is still if cutting the board will cause a large enough change to be able to detect it.   I think we already have that answer.   Looking at that data, it does seem very bad.    I suspect a crack and reflowed the joints.  Connectors were clean.  Terminator appears fine.  May have cracked it at some point or it was never soldered in the first place.  It's been badly abused. 


originaltest1_new: Showing all the data from test1 prior to the cut compared with the data I collected tonight. 

originaltest1: Showing all the data from test1 (prior to the cut) normalized to trace1.   Looks bad.

HAND: data from tonight showing hand tightening, normalized to trace1.

TORQUE: data from tonight showing torqued, normalized to trace1.

combine:  All the data from tonight, normalized to the mean. 

Guessing a bad joint.

[MartinL]

Just want to echo the point about cracking. The ceramics used in SMT MLCCs are very brittle and can easily be cracked by flexing of the PCB, particularly if the board is thin and the capacitor is tall.

A while ago I had to diagnose a small collection of failed 60GHz radar boards. After a lot of head scratching, the thermal camera revealed that some of the decoupling MLCCs in the power supply section were getting hot. Removal and measurement showed them to be shorted; replacements worked fine. All were top-spec AEC-Q200 genuine Murata parts.

The cause was cracking from mechanical stress on the board, but the damage was almost invisible. See attached photo.

The only mechanical stress these boards had been exposed to was being pushed onto stacking connectors of a mating board by hand.

[joeqsmith]

I looked at the free version of Sonnet.  It was too limited to get anything working.  So I tried an old version of Ansoft.  I was able to get a simple EM simulation to run and even tried creating a model based on the Touchstone file.   Both ran fine however, once again it appears too limited to allow simulating what the OP had asked about.  I am not aware of any other free tools.     

http://www.gunthard-kraus.de/Ansoft%20Designer%20SV/English%20Tutorial%20Version/index_english.html

[G0HZU]

I looked at the free version of Sonnet.  It was too limited to get anything working. 

If you register the Sonnet Lite version you get a free increase from 1Mb to 32Mb memory. I assume Sonnet will send you a free flexlm licence locked to your PC to allow the 32Mb memory upgrade.

32Mb is quite generous and should be more than adequate for the stuff you are looking at.

[joeqsmith]

I am not familiar with any of these tools but with your experience, are you sure it would even be able to run this little demo?   It looked like there was no way to split the ground plane.  I was going to attempt to remove it and add another signal layer.   I also wasn't sure if I could import the Touchstone file into the EM model. 

With you having the full blown tools and the experience with them, how difficult would it be to set up the simulation and run it?

[G0HZU]

I think the Lite version will be able to do the ground plane split and model an air layer above and below the PCB.

One limitation will be that the cap model is for a perfect capacitor so there will be no package inductance or loss in the cap model. Also, the EM simulator can't model the interaction between the PCB and the body of the cap unless the cap is crudely modelled as a brick of dielectric. I think this is only supported in the full version. Even then I'm not sure how realistic this will be because the real cap body will also contain multiple inner plates of metal.
The s2p models from ATC will be taken over a PCB with a regular ground plane so this won't be quite right either if you then cut away the groundplane in Sonnet.

Try registering it to get 32Mb and then set up the box, the layers and then add the metal for the top microstrip and add the ideal cap. You can then edit the groundplane by adding an air layer below the main PCB. This creates a lower layer for your PCB that you can edit. When you do this you have to draw the PCB ground plane details yourself as it will start with no metal on this lower PCB layer.

[joeqsmith]

Can you split the ground plane with the full blown version?

I see no reason why a capacitor would be required other than this is what the OP had asked about.   They haven't chimed in, so I doubt have any interest in it.   Still, I'm curious how close any of these simulators would predict the effects.   Do you have any better ideas how to proceed?   

Based on the little I have no played with these different simulators, I am thinking just go with their first test:

1. A 50-ohm microstrip with two SMA connectors, far-end terminated by 50-ohm coax load. One board has solid ground plane and another has cut out under the center conductor for impedance compensation.

The problem with Sonnet would be splitting the plane.  I suspect the same is true for Ansoft.   

[G0HZU]

You can split the ground plane with both the Lite and full versions of Sonnet. Even if you don't register it and use 1Mb memory you can do these things in Sonnet Lite although you would be limited in PCB size and by how much metal you can put on the board before it goes over 1Mb. I think the Lite version also only allows a few layers before it hits a limit but this won't apply in your case as you don't need many layers.

[coppercone2]

solder very thin long dummy resistors in random places of the PCB to see deflection, if there is stress on the board you should see bowing under a microscope.

[joeqsmith]

As I said, there appeared to be no way to change the ground plane.   The only work around I could come up with was to create a separate signal layer and use that as the ground but the simulator complains about the number of layers for the free license.   But again, you use it on a professional level and I expect you could knock it out in a half hour or less.  Or, is the tool far more complex to use? 

[joeqsmith]

From the manual:

GND Level: You can place polygons on the GND level, but they have no effect
because this level is already completely metalized. However, cases do exist in
which you may want to place a polygon on the GND level in order to place a via
or a dielectric brick there.

Obviously, this is not true as you use the tool.  I suspect I am just not understanding what this statement is suggesting.

[G0HZU]

What they are referring to there is the 'box' GND. You can't edit this because it is meant to be a perfect ground at all times. You can think of the EM simulation happening inside a perfect metal box that is a perfect ground everywhere on the walls and the bottom face. However, just like you can put a 2 layer PCB inside a box you can put a two layer PCB inside the perfect Sonnet box.

[G0HZU]

In other words, the simplest PCB simulations let you use the box ground as the bottom layer of your PCB. I think this means the simulation will use less resources and will run faster. You can connect vias to the box GND but you can't edit the box GND layer 'artwork' because it has to remain perfect. If you want a 2 layer PCB where you can edit the lower layer to make it less of a perfect ground plane then you have to float it above the box ground just like you would in a real box.

[joeqsmith]

If you want a 2 layer PCB where you can edit the lower layer to make it less of a perfect ground plane then you have to float it above the box ground just like you would in a real box.

Which is what I was suggesting when I wrote:

The only work around I could come up with was to create a separate signal layer and use that as the ground but the simulator complains about the number of layers for the free license.

  It seems that the free license will not allow for that added layer.   This new floating ground could be attached to the boxes ground with vias as well.  Otherwise, I suspect there would be a limitation on the number of ports.  It's such a simple project but seems to require a license.   

I added a second signal plane with the free version of Ansoft and I don't think the license was a problem.  I ran into problems when trying to simulate the capacitor rather than using a lumped model.  If I remove that constraint, it may be possible to use that tool. 

[joeqsmith]

Do you actually have the full license for Sonnet, or are you using one of the limited licenses?   I should have asked but assumed with it being for work you had the full blown license. 

[G0HZU]

The works licence has full memory and a few basic options including the Genesys co-simulation option. This was purchased back in 2004 and I use the Sonnet engine via Genesys. In other words I do all the PCB design and circuit design in Genesys and then Genesys asks Sonnet to simulate the PCB layout. The results get automatically sent back to Genesys and Genesys graphs the results.

Have you checked what metal layers you can see? You should have 0, 1 and GND where GND is the box GND and layer 1 is your editable ground. Layer 0 is the top microstrip layer.

[joeqsmith]

Makes sense.  I saw they had support for other layout tools as well as DXF.  The DXF requires the LitePlus license.  It gets you 6 ports and a few other features.     

They claim 2 metal layers with the Lite, which I would have assumed did not include the box.  They also allow 4 ports so you would think the design could just float in the box.  Guessing I am missing something.

[joeqsmith]

Even two more vias will throw it over the 32M.   The $500 license wouldn't seem to add enough to make it worth while. 

[joeqsmith]

Showing estimation with 8 vias and also attempting to run it. 

32Mb is quite generous and should be more than adequate for the stuff you are looking at.

While its the basic coplanar with a slit in the ground plane, there's no point in spending the time to make everything correct.   I just wanted to get some idea how much memory it will require.   From your comment it would seem like you felt it wouldn't be a problem.  Maybe I am doing something wrong.   

[G0HZU]

The original exam question involved relieving the ground under microstrip. Search for how many times microstrip gets a hit on this thread. Why are you (loosely) adding coplanar waveguide components to the simulation when this isn't necessary? Your circuit is just eating up memory for no reason.

I suspect it would be possible to do the microstrip simulation with just 1Mb memory with a little care.

[G0HZU]

If you want to move the goalposts to (grounded) CPW then try ditching the vias and then skinny up the box and just have a thin coplanar strip either side of the main signal trace and make sure the two CPW traces extend to the walls of the box.

[joeqsmith]

The original exam question involved relieving the ground under microstrip. Search for how many times microstrip gets a hit on this thread.  Why are you (loosely) adding coplanar waveguide components to the simulation when this isn't necessary? Your circuit is just eating up memory for no reason.

I suspect it would be possible to do the microstrip simulation with just 1Mb memory with a little care.

If you want to move the goalposts to (grounded) CPW then try ditching the vias and then skinny up the box and just have a thin coplanar strip either side of the main signal trace and make sure the two CPW traces extend to the walls of the box.

I suspect there was a bit of miscommunication was all.  If you take the time to go back and read the first couple of posts in this thread, while the OP was certainly proposing microstrip,  I talk about using a coplanar design.  I show pictures of the test boards and provide dimensions for the design.  I have not changed to a coplanar design, rather it was that way from the start.     

It seems it wasn't clear to you that the goal was to see how a simulation would compare with the physical hardware.   Certainly hardware could be built based on the limitations of the simulator but my intent has always been to simulate an existing design.    You wrote early on about the choice of using that ATC device.  I suspect that you failed to understand that a test board had already been built up with one from a prior experiment.   

If you would like to simulate what the OP had first proposed using the microstrips and capacitors, again I welcome seeing a parallel effort. 

[G0HZU]

You probably can still include vias and GCPW and keep within the 32Mb limit. You seem to be adding too many ports which will be wasting memory for one thing. Also there are various ways to reduce the memory requirements.

Learn to use the tool before giving up on it so soon. However, I suspect your mind is already made up and I think I know how this movie will end no matter how much I try and help you.

[G0HZU]

Try making the layout symmetrical and try playing with coarse meshing. There are other memory saving tricks as well. I don't think you need to add ports to the lower layer in this case (1.5GHz) as the bottom layer is grounded along the sides of the box and you can float it close to the box GND. This will save some memory.

[MartinL]

When I last looked at Sonnet Lite, you couldn't simulate a two-port GCPW board, because modeling one actually requires 6 ports in the simulation (at each end of the board you need ground-signal-ground: 3 ports). The Lite version only gives you 4 ports. So you can model a two-port or even four-port board if you use microstrip feeds, but only a one-port one with GCPW.

[G0HZU]

You definitely need lots of ports for classic coplanar waveguide but I think a run of grounded coplanar waveguide can be modelled just fine with 1 port at each end of the run. It is important to make sure the coplanar shapes touch the sidewalls of the box.

I'd be interested to know how (and why) you modelled it with 3 ports at each end. That number of ports would be fine for classic CPW but not required for GCPW?

[Marsupilami]

Hey @joeqsmith

Sorry, I only read about half of this thread, but simulating from that cap s2p is problematic. If you have access to any tools that can approximate sNp networks with a spice circuit that would be a good step. Maybe even you could do it manually just putting extra reactive elements to get the resonances visible on the s-par plot.

I have a fairly usable 3D EM simulator but it can only deal with simple lumped components or a SPICE subcircuit. This one is using simply the ESL, ESR and Ceff of the cap. This won't show the weird parasitic effects.

[eb4fbz]

One thing to watch out for is that the ATC s-parameter models are taken over a PCB substrate so I'm not sure it is a good idea to use them anyway. These capacitors behave differently when mounted vertically or horizontally and this is because the metal structure within the cap body acts a bit like a transmission line when mounted over a given substrate. This is part of the reason these caps have sharp resonances and they often aren't suitable for wideband design work.
 
For your EM simulations you can try playing with (free) Sonnet Lite but I think it only allows a perfect capacitor model in the Lite version. It probably will let you play with the groundplane but I've not really used the Lite version very much.

One thing worth noting is that it can sometimes be a good idea to deliberately use fatter pads (compared to the ideal microstrip width) for the component if it has a tiny amount of series inductance. The fatter pads and the series inductance form a pi network and this can help improve the s11 response up at UHF.

At work I use Genesys and Sonnet combined together for stuff like this. I've used various EM simulators and Sonnet always comes out top for the most critical tasks. It can do multi layer simulation and can allow custom groundplane shapes with gaps. When used with Genesys it allows s-parameter models allowing very good simulation of LNAs and lumped+ distributed filters. It is a very powerful combination in my opinion.

I'm not really sure what you are trying to do but I suspect there will be cases where removing part of the groundplane will actually make things worse and sometimes it will help. A lot depends on the component and the pad shape it requires. Also, a lot depends on the chosen PCB material in terms of dielectric constant and substrate thickness.

https://www.modelithics.com/Model/SubstrateScaling

[MartinL]

You definitely need lots of ports for classic coplanar waveguide but I think a run of grounded coplanar waveguide can be modelled just fine with 1 port at each end of the run. It is important to make sure the coplanar shapes touch the sidewalls of the box.

I'd be interested to know how (and why) you modelled it with 3 ports at each end. That number of ports would be fine for classic CPW but not required for GCPW?

Ah, you're quite right - I've just looked into it again and what I said is true for CPW but not for GCPW. That makes the Lite version quite a lot more useful actually - I'll need to have a proper play with it. Thanks!

[Marsupilami]

I was playing around a bit more with this.

1.5mm thick FR4. Trace is 2.5mm wide with 1.5mm gaps. I made a giant-ass 3x4mm cutout under the cap and it still has very little effect.
I'm guessing the contribution from the bottom ground is relatively low in this configuration plus even at 6GHz a 3mm gap is about 10th of the wavelength so it can find its way around easy.


I used a SPICE model for the cap from Murata because that's what my simulator likes. Apparently they have the parallel resonances modelled in it. (2.7 and 4.5GHz)
I found this article that describes how the capacitor orientation effect the parallel resonances. This was new to me, quite interesting.
https://www.johansontechnology.com/srf-prf-for-rf-capacitors
It explains the missing resonances from the AVX s2p as they take those in the vertical orientation so the odd parallel resonances are out. PPI has a matching cap for the AVX 100B series (1111P) and they actually provide S-Parameters for both horizontal and vertical orientation.

[joeqsmith]

I see no reason why a capacitor would be required other than this is what the OP had asked about.   They haven't chimed in, so I doubt have any interest in it. 

You could try removing the capacitor from the equation.  Maybe just plot the before and after the slit are added.   Will your simlator support Smithcharts?       What about exporting to Touchstone?   

If you stay with the dimensions/material I show,  I could attempt to replicate it in hardware. 

[joeqsmith]

Something like this? 

Shown sweeping the gap in 5 mil increments, exporting to Touchstone and importing to METAS.  The dimensions are still a swag. 

[Marsupilami]

That looks good. Is that Sonnet?
What dimensions did you use? Er of the dielectric?
I can do that too without the cap and export touchstone. That'd be a good comparison.

[joeqsmith]

Basically what I had shown in AppCAD, Er 4.6, 62 mil, 1oz copper, FR-4.   Using about a 200 mil width for the slit.

[Marsupilami]

Here's mine. It's with no slit and a 1x5mm slit.
I did a parameter sweep to but only with reduced grid resolution as I didn't have the patience for that. (Time domain simulation has it's downsides.) How things move around is similar.
Do you have s2ps for your matching results?

[joeqsmith]

Thanks for taking the time to run it.   It's good to have some sort of sanity check.

I have continued to play with the various free simulators available.    Not using any of these tools on a professional basis and having virtually no experience with any of them, take my post accordingly.

The free version of Sonnet (15.53) is from 2014.  They are up to version 17 now.  Note how they promote faster sims with 17 vs 16.  For just trying to simulate a trace, 15 is very slow. 

https://www.sonnetsoftware.com/products/sonnet-suites/new-features.html
https://www.sonnetsoftware.com/products/sonnet-suites/suite-prices.html

Sonnet has created Touchstone files with the frequencies out of order.  The tool should never do this as the standard doesn't allow it.   I've also seen where it would append data to the Touchstone files rather than create them clean.  The memory provided is very limited and prevents trying different approaches.   Many of the features are also disabled.   Sure it's free but if their goal of making a free package was to sell products, I would think they would want to showcase what they have to offer today, not where they were seven years ago.

I am not sure Looking at the data it produces, what to make of it.   Something really strange happens at 3GHz.    I've played a bit with the various settings to try and tame it. 

[joeqsmith]

The BLACK trace in the following data was collected using the same mechanical dimensions, materials and settings, except the range was increased to 6GHz. 

I then tried various combinations of coarse no edge detection, symmetry, fine edge, and cell sizes.    While they appear have some effect, none play into the overall wave shape.

What is really interesting is I swept one of the unmolested test boards which again is roughly represented by the AppCAD screen shot I posted.  Marsupilami's data is the BLACK trace.  The PNA is BROWN.   I think we got lucky they would match this close.   The PNA's s2p Touchstone file is attached. 

I manually adjusted the boards thickness, Er and loss to try and achieve the same shape.  The numbers I am using are not even in the ballpark.   

I also removed the vias, then removed the floating ground plane.  This also had no effect.   There is a note in the manual:

Please note that when the value of the S-parameters is close to 1 (0 dB) over the entire band you may have small ripples or oscillations in the S-parameter values. This is due to the rational fitting model having too many degrees of freedom when trying to fit a straight line. If this is a problem, it is recommended that you analyze the frequency band in which this occurs with another type of sweep.


I had been using linear sweeps as well as exponential.  Both have no effect on the shape.    Another part in the manual talks about the box resonance.  Running the tests, it shows there are none.   Changing the distance to the box and using free space also have no effect on the shape.   

[joeqsmith]

As much as I like that METAS software,  it doesn't appear to support Smithcharts.  Attached is AppCAD plotting data from the PNA, Marsupilami and Sonnet. 

The Sonnet data is using the settings from the AppCAD coplanar drawing.   
   

[Marsupilami]

Interesting.
What's easy to figure out first I think is the S21 phase response. On your PNA measurement is the extra length for the connectors compensated for or is it still in? Or did I screw up the length of the board. I think I did 28mm. (1.1" ?)
It's 62 vs 88 degrees per GHz. (The Sonnet result being around 50/GHz maybe?)
This thing: https://chemandy.com/calculators/coplanar-waveguide-with-ground-calculator.htm tells me that the effective Er is about 3.4
Than this: https://www.microwaves101.com/calculators/873-wavelength-calculator says that 1GHz wavelength is 162.7mm
Based on that:
Mine: 28.02mm
PNA: 39.77mm (assuming a uniform Er=3.4 line, see below)
Sonnet: ~23mm ?

If your board is indeed 1.1in and the SMA connectors are on it, which I assume have a teflon dielectric with Er ~ 2 then  7.5mm@Er=2 + 28mm@Er=3.4 + 7.5mm@Er=2 actually gets us 88degrees @ 1GHz would explain the PNA S21 phase slope perfectly.

I would try to figure out if this is correct so far and the look into why Sonnet thinks the section is shorter.

[Marsupilami]

On a related note it's ridiculous how inaccessible these software are. I started looking for one about a year ago and went through the 7 stages of grief realizing what my options were.
At some point I even considered making a project out of writing my own using an open source library or code my own front end for OpenEMS. I wasn't looking at Sonnet as I wanted a full 3D solver but I tried like a dozen and talked to a bunch of sales people. It's one thing that stuff is expensive but the big names don't even do perpetual licenses anymore so you have to be actively making a lot of money with it in order to keep up with the license costs. I ended up with XFdtd which might not be the most optimal for some problems (time domain solvers struggle with high Q stuff) but at least it "only" costs as much as a car not as much a house and they offered a reasonable lease to own plan. I really wanted to learn something at home at my own pace, the return on investment is questionable and I'm not going on vacation for a while.

[MartinL]

I was just having another look at the state of interfaces to OpenEMS, and found an example in pyopenems for simulating a ground cutout under a capacitor:

https://github.com/dlharmon/pyopenems/blob/main/examples/capacitor_ground_cutout.py

I haven't set things up to run this yet but it might be worth trying.

[joeqsmith]

Interesting.
What's easy to figure out first I think is the S21 phase response. On your PNA measurement is the extra length for the connectors compensated for or is it still in? Or did I screw up the length of the board. I think I did 28mm. (1.1" ?)
It's 62 vs 88 degrees per GHz. (The Sonnet result being around 50/GHz maybe?)
This thing: https://chemandy.com/calculators/coplanar-waveguide-with-ground-calculator.htm tells me that the effective Er is about 3.4
Than this: https://www.microwaves101.com/calculators/873-wavelength-calculator says that 1GHz wavelength is 162.7mm
Based on that:
Mine: 28.02mm
PNA: 39.77mm (assuming a uniform Er=3.4 line, see below)
Sonnet: ~23mm ?

If your board is indeed 1.1in and the SMA connectors are on it, which I assume have a teflon dielectric with Er ~ 2 then  7.5mm@Er=2 + 28mm@Er=3.4 + 7.5mm@Er=2 actually gets us 88degrees @ 1GHz would explain the PNA S21 phase slope perfectly.

I would try to figure out if this is correct so far and the look into why Sonnet thinks the section is shorter.

I would have expected the two simulators, being fed the same data would have yielded roughly the same results.  I had assumed you had used the data from the AppCAD drawing  but it sounds like you had not used these values.    This make much more sense now why there is such a difference between the two.   

Yes, all the dimensions were in inches.  Yes, 1.1" or 27.94mm.   

https://www.eevblog.com/forum/rf-microwave/experiment-testing-the-effects-of-releaving-ground-plane-beneth-a-component/msg3609708/#msg3609708

I wasn't too concerned with the data from the PNA beyond seeing if any of the data was even in the ballpark.  Eventually I will go back an measure everything but for now I am just trying to understand why the results from the simulators are so different.

You could provide details about your simulation and I would change my model or you can use the data from AppCAD and see what you come up with.   Maybe we could do both as it would not hurt to run more than one test case.   

[Marsupilami]

No no I totally used those values from your screenshot. I just rounded stuff to near metric units as my European brain can't process imperial properly.

Trace width: 2.8mm
Gap width: 2.1mm
Dielectric thickness: 1.5mm
Copper thickness: 0.09mm
Er of dielectric: 4.6
Length of the section: 28mm

[joeqsmith]

No no I totally used those values from your screenshot. I just rounded stuff to near metric units as my European brain can't process imperial properly.

Trace width: 2.8mm
Gap width: 2.1mm
Dielectric thickness: 1.5mm
Copper thickness: 0.09mm
Er of dielectric: 4.6
Length of the section: 28mm

Rechecking your work,
The copper is 0.00135" or 0.03429mm.    0.09mm - 0.0035", I suspect that was a typo in the conversion.
The dielectric is 0.062" or 1.5748mm.  I would round to the nearest, or 1.6mm.

If you don't mind changing it, then run a few different test cases (without the gap).  Post your Touchstone files.  I will then repeat your conditions and post the results as well.  I will change to metric to make it easier for you.   

[Marsupilami]

If you don't mind changing it, then run a few different test cases (without the gap).  Post your Touchstone files.  I will then repeat your conditions and post the results as well.  I will change to metric to make it easier for you.

I will but I doubt any of those differences would get us significantly different results.
I'll set up fixed grid points too to get better aligned with the ideal geometry.

[Marsupilami]

I haven't set things up to run this yet but it might be worth trying.

Have you done anything else with it? I feel it's too late for me to dig into it but I'm still curious to hear about some first hand experience with OpenEMS.

[joeqsmith]

For the length wise, I am using a cell size of 0.005".  For the width, I was using 0.001". 

I too am interested in seeing results from OpenEMS.  I stayed away from it due to it being script driven.  Similar to creating SPICE netlists by hand rather than being schematic based.   Maybe there is a front end for it.   

[MartinL]

There isn't any polished frontend as exists for the commercial packages. There's Qucs-RFLayout which allows you to put together a schematic in Qucs and then export to openEMS script. It currently only supports microstrip structures though, not GCPW.

And there's a FreeCAD plugin that can export geometry to openEMS.

The MATLAB scripting interface is actually already a "frontend". the actual interface to the OpenEMS solver is a C++ API.

There's also two python libraries, pyems and pyopenems, which provide a higher-level API than the built-in bindings.

I've always thought there's a real opportunity for someone to build a nice GUI on top of openEMS - it could be a game changer in making these sorts of capabilities more accessible. But it would be a big project with a fairly small potential userbase, many of whom either already have access to commercial tools, or can get by with the existing interfaces.

I'll see if I can get something running that corresponds to the test case you have.

[Marsupilami]

Here are the results of another run.
I changed the dielectric thickness to 1.57mm and the copper thickness to 0.035mm.
I also aligned the grid points to the trace features.




The return loss looks significantly different on a magnitude plot but I think below 25dB I'm hitting some numerical limits. I'd have to play around more with meshing and waveguide port settings.
The transmission changed very little.

[joeqsmith]

I had thickened the Cu layers as well, no difference.   I removed the vias to speed the tests but saw no major change.   I noticed you are using 4.  I could add them back in if you want to provide details about them.     

The width of each top side plane is 351mils or a total width of 981mils 
Cu conductivity is set to 5.8e7 S/m
FR-4, 62 mils thick, Er 4.6, Loss Tan 0.02, Conductivity 0.0 S/m, Mrel 1.0,  Mag Loss Tan 0.0
Ports resistance is set to 50 ohms (license prevents any changes)
I'm using an inch from the top of the CPW to the box, air dielectric
I'm not using the de-embed feature, symmetry

The attached Touchstone is with the above setting and matching the AppCAD drawing.   I doubt any of this will matter and suspect there is some difference in the simulators that causes this error.   

If  you want to see if the two simulators will show somewhat of a trend, I reduced the width of of the signal trace from 113 mils to 16 mils. No other changes were made.   

****
Using the baseline from AppCAD, I then changed the dielectrics thickness to 10mils. 
 

[joeqsmith]

Sweeping the gap from fully closed in 100 mil increments.   Gap is anchored to the left edge and opens towards the right as shown.   Slot=550.0 is closed.  The other settings are the same as before in AppCAD. 

I wouldn't expect the wave shape to change as it does.   

Hopefully this give you enough test cases to try.   

[joeqsmith]

Still using the symmetry mode but moving both ends of the gap to avoid the diagonals, I had hoped some of the data would make a little more sense.   I also thought it may reduce the memory requirements and speed up the simulation. 

[neilhao]

Oh, I just did the similar work related SMA connector in UWB application. I have to use slot for eliminating the impedance mismatching between PCB trace and the SMA footprint.
My two cents:
https://uniteng.com/wiki/doku.php?id=uwb:evb#uwb_front-end_design

[joeqsmith]

https://www.simberian.com/

Similar experiments with SIMBEOR. 

[Marsupilami]

Still using the symmetry mode but moving both ends of the gap to avoid the diagonals, I had hoped some of the data would make a little more sense.   I also thought it may reduce the memory requirements and speed up the simulation.

Did you come up with anything conclusive since?
Work went crazy in the past couple of weeks, I didn't have any time, but I'm still curious to see a comparison to measurements.

[joeqsmith]

Still using the symmetry mode but moving both ends of the gap to avoid the diagonals, I had hoped some of the data would make a little more sense.   I also thought it may reduce the memory requirements and speed up the simulation.

Did you come up with anything conclusive since?
Work went crazy in the past couple of weeks, I didn't have any time, but I'm still curious to see a comparison to measurements.

Sadly, I was never able to make any sense of it.   I suspect I am just asking too much out of the free tools.   It's a very interesting topic and it would be fun to experiment more with it.  Sadly, I was not able to find limited versions for the more modern tools and their costs far exceed my hobby budget.