First RF PCB Design

[x4ce]

Hi,

I am an amateur in the field of PCB design and my experience includes multiple PCBs design of basic digital electronics and STM microcontrollers etc. I have got them manufactured by JLCPCB and they worked, successfully. This is my first basic RF PCB designed in KiCad and requires some guidelines before I go for assembly etc.

The frequency signals range from 250 to 500MHz.

What I know and have done so far:

The lengths of traces carrying the high-frequency signals should be shorter than 1/10 of the wavelength of the highest frequency taking into account the propagation delay due to PCB.

The traces for high-frequency signals should possibly remain straight or should have a radius of curvature.

The width of high-frequency signals should be 3mm in order to match the impedance of 50ohm for PCB of 1.6mm thickness & FR 4.6.[/li][/list]



The guidelines required are:

1. Is the ground fill zone/ place fine on the top layer with RF signals?
2. If ground fill/ plane is not required on the top layer then I need to put via holes for ground pads. Any criteria for this? There should be at least 2 via holes? Distance between them etc.?
3. The pads etc. do no match the trace width (0.3mm), would they affect the impedance matching, and, if so, what is the solution?
4. Should I place a guard ring around the whole PCB or between the input and output antennas?[/li][/list]

I have attached the initial PCB design with component detail on the silk screen for ready reference.

I will be grateful if someone could guide me.

Regards
Shahid

[TheUnnamedNewbie]

I think you should start with sharing the schematic. It is too much work for me to bother looking at a PCB and try to figure out what traces are doing what.

The frequency signals range from 250 to 500MHz.

This isn't too high yet.

What I know and have done so far:

The lengths of traces carrying the high-frequency signals should be shorter than 1/10 of the wavelength of the highest frequency taking into account the propagation delay due to PCB.

This is a common rule of thumb, but the main thing is not that they should be shorter, rather that if they become longer, you should start taking the line impedance into account.

The traces for high-frequency signals should possibly remain straight or should have a radius of curvature.

At 500 MHz, this doesn't really matter too much.

The width of high-frequency signals should be 3mm in order to match the impedance of 50ohm for PCB of 1.6mm thickness & FR 4.6.

That is quite a wide trace. I would consider going for a 4 layer PCB for this kind of design, as routing without disturbing your return currents will be challenging at best on a 2-layer PCB. A 4 layer PCB will also reduce your 50 ohm trace width significantly and as a result make the entire routing process more manageable.

Most of the issues you talk about in your questions are minor, likely even insignificant, at 500 MHz, unless you are doing ultra-high-precision measurements or super sensitive measurements (at which point you should stop using rules of thumb anyways and switch to using electromagnetic simulators).

500 MHz has a wavelength of like 60 cm in free space, so unless your PCB is massive, and don't break your return currents, things will be fine.

[x4ce]

Thanks for the reply and guidance.

I have shared the schematic for your ready reference.

As far as the trace width is concerned, it was a typing mistake and the correct trace width is 0.3mm.

Please if you could further guide for the following concerns:

The guidelines required are:

1. Is the ground fill zone/ place fine on the top layer with RF signals?
2. If ground fill/ plane is not required on the top layer then I need to put via holes for ground pads. Any criteria for this? There should be at least 2 via holes? Distance between them etc.?
3. The pads etc. do no match the trace width (0.3mm), would they affect the impedance matching, and, if so, what is the solution?
4. Should I place a guard ring around the whole PCB or between the input and output antennas?

Thanks

[T3sl4co1l]

There's no ground vias, and only a couple thru-pins connecting the layers?  Yipe!

Roughly speaking, a via per pad, plus vias flanking especially longer traces, plus vias scattered around evenly (in a grid, error diffusion, whatever you like) will greatly improve things.

Tim

[kml183]

Hi! Cool design! I am a RF newbie as well. 

Like the TheUnnamedNewbie said, you might want to use a 4 layer pcb stack up like the JLC7628 or JLC3313. Those are the two main controlled impedance stackups that JLCPCB offers as well.

As far as the trace width is concerned, it was a typing mistake and the correct trace width is 0.3mm.

You are also creating a co-planar strip line with the top copper pour. If you want to do this, (as I understand there are some benefits like lower trace losses for higher power), you need to make sure the spacing between the trace and copper pour is correct as well. See the attached image for some calculations with the KiCad transline calculator.

To answer the rest of your questions.

2. With RF stitching vias there seems to be many rules of thumbs that people use. The one that I have been using is the grid spacing should be at maximum 1/6 of your max wavelength which for you is 5 cm (c / 500Mhz / 12). The other one that I have seen for higher speed designs ( > 1G ) takes into account the velocity factor which is 1 / (e_r ^ -2 ). E_r is the effective permittivity of your dialectic (4.6 for FR4) so something like (velocity_factor * c / 500Mhz / 12). Either way if you have vias spaced closer together you are fine. 

3. For your max frequency it won't make much of a difference. So I wouldn't worry about it. What you can do is use traces of varying sizes to create a gradient from your larger pads down to the 0.3mm trace width.

4. You can if you want to. It won't make much of a difference because your PCB is only using 1 signal type. Guard rings are more useful for mixed signal boards to combat interference between the signals. I would just make sure that my vias stitching the GND planes together extend close to the end of the PCB.

[x4ce]

Thanks for the suggestion.

I have made a whole new design of 4-layer with 0.3mm signal trace width for RF paths. The right side of the board includes two booster converters, op-amps, and DAC etc. I will be using JLC7628 stack up so my stack is:

1 > Signals (Left RF and Right mixed)
2 > Ground
3 > 5V
4 > Signals with ground fill.

I have attached my design to review so if you could find potential flaws, or suggestions to improve the design.

Regards
Shahid

[kml183]

From a EMI perspective this will probably work for the frequencies you want. Here are some things that might help reduce EMI, increase signal integrity, etc:
 
- Usually you want to keep components as close as possible to reduce parasitics. Leave just enough room that you can solder with your process of choice.
- It looks like you only have a few components that use 5V. It would be better to just route a 5V trace (very thick) between those parts. That way you can use layer 3 as another ground plane. This will increase the signal isolation.
- The amp should have some sort of LC filter on the DC bias pin (5V). This will just filter out any high frequency noise from the power supply.

In terms of your design, I am not sure what the update schematic looks like but depending on what the input RF signal you might have some issues. Are you just summing the the powers between that input signal and the one you generate? There isn't any filtering present so if there are harmonics or some other frequency component in the input, that will mess up what you expect from the summation. I am not sure if ADP-2-4 can take a DC biases signal. Regardless, the max input power is 1W so with the DC bias I think that will decrease how much power your RF signal can have before going into it.

[x4ce]

From a EMI perspective this will probably work for the frequencies you want. Here are some things that might help reduce EMI, increase signal integrity, etc:
 
- Usually you want to keep components as close as possible to reduce parasitics. Leave just enough room that you can solder with your process of choice.
- It looks like you only have a few components that use 5V. It would be better to just route a 5V trace (very thick) between those parts. That way you can use layer 3 as another ground plane. This will increase the signal isolation.
- The amp should have some sort of LC filter on the DC bias pin (5V). This will just filter out any high frequency noise from the power supply.

In terms of your design, I am not sure what the update schematic looks like but depending on what the input RF signal you might have some issues. Are you just summing the the powers between that input signal and the one you generate? There isn't any filtering present so if there are harmonics or some other frequency component in the input, that will mess up what you expect from the summation. I am not sure if ADP-2-4 can take a DC biases signal. Regardless, the max input power is 1W so with the DC bias I think that will decrease how much power your RF signal can have before going into it.

Thanks for the suggestions and I will do consider them t incorporate them in the design.
The ADP-2-4+ is acting as a splitter to power out RF antenna and to Frequency Mixer (ADE-2ASK) which will perform sort of demodulation with the RF input.  Here I have attached the original schematic for your ready reference and I may be wrong explaining to you. If you see any potential issue please let me know.

Regards
Shahid

[kml183]

If this is a proven reference design, it will work. If not I would definitely recommend simulating this in LTSpice or Qucs-s. There isn't any filtering on that antenna input, so if you don't get the exact spectrum you want, that will cause some issues for this design.

[Bud]

Your U6 mixer will be overdriven on its LO port from U5. Lets see why. By the datasheets of the devices used, the output of U1 is +6dBm. After the attenuator U2 the signal going into the amplifier U3 is -4dBm. Gain of the amplifier U3 in the 500MHz range  is roughly 23dB. The output of U3 is going to output +19dBm. This is already in the 1dB compression area of U3. By other words, at this level U3  distorts the signal, producing harmonics.
Now, the +19dBm signal goes through the power splitter U5, and the outputs on each shoulder (to the antenna and mixer) will attenuate by 3dB by the power splitting action, so the signal levels at the antenna and the mixer become +16dBm. Do not know if you have any requirements to the power into the antenna, but the mixer U6 by the datasheet needs +7dBm for optimal work. And you feed +16dBm into it, which is 9dB higher.

To remediate this RF power budget issue and to improve interstage matching I would insert a 3dB attenuator after the amplifier , a 6dB attenuator between the splitter and mixer, and a 3dB attenuator before the antenna port. The antenna attenuator will provide RF isolation of antenna non optimal impedance from the rest of the circuit.

If you want a cleaner signal at the antenna, you should attenuate the signal going into the amplifier so its output is 6...10dB below the amplifier's 1dB compression point. Then recalculate the signal levels at the mixer LO port and see if an attenuator needs to be used to bring LO signsl to +7dBm level.

[x4ce]

Thank you very much for replying.

I have replaced JTOS with CVCO55CW VCO which gives a +3dBm output power and amplifier will give 22.1dBm amplification at 500MHz, precisely. At the splitter I would end up +12dBm at the antenna and mixer inputs. I will follow your suggestion to reduce output at +6dBm at mixer input and antenna. Besides, loss due to U4 (Bias-tee) is negligible?

Thanks

[Marsupilami]

Shahid,

I think this is going to work from the layout perspective, because of the size of the board and the 500MHz frequency, so take this only as a thought provoker and maybe to factor in for your next board.

I think the thin traces you choose on the 4 layer stackup are actually worse then what you started with. It's true that the trace itself is closer to 50Ohms but coming out of the connector in a few mm you'll hit the pad of the capacitor and the pad of the splitter and those are large and will present a significant impedance discontinuity (which is what's causing reflections, thus your return loss being worse) There are multiple ways how to handle this properly. What I might do is pick a 0.6mm 2 layer board and do ~1.5mm traces with solid ground on the back. You can replace for example your bias tee to an RCBT-63+ that has a similar scale footprint as the splitter, and I'd look for replacement for the other tiny components as well. The capacitors are easy, the IC pad size is close enough. The point is not to have as much 50Ohm trace as possible, but to have as few and little discontinuities.
Look at the datasheet of the splitter for example, there's layout guidance there.
I think you also should have a bunch more of GND vias around GND pins of components. Think about the current return path. If an IC has an RF pin and some GND pins around then the return current will want to go from those ground pins to the bottom layer and to under the RF trace. Make sure it has the shortest, lowest impedance route possible for that.

Another quick thing is make sure you don't have silk screen over your pads. Most fabs will check for that and remove it anyway but I've seen boards made that way and if it happens you'll have to scrape it off before you can solder your parts.

Good luck!

[T3sl4co1l]

Shahid,

I think this is going to work from the layout perspective, because of the size of the board and the 500MHz frequency, so take this only as a thought provoker and maybe to factor in for your next board.

I think the thin traces you choose on the 4 layer stackup are actually worse then what you started with. It's true that the trace itself is closer to 50Ohms but coming out of the connector in a few mm you'll hit the pad of the capacitor and the pad of the splitter and those are large and will present a significant impedance discontinuity (which is what's causing reflections, thus your return loss being worse)

Can typical VNAs even measure the "significant" impedance discontinuity of those pads at 500MHz?

Tim

[Marsupilami]

Can typical VNAs even measure the "significant" impedance discontinuity of those pads at 500MHz?

Tim

That's a good point. Let me see. For a 1.5x2mm pad over 0.21mm of FR4 I get 530fF without edge effect. If I didn't mess up the calculations somewhere and assuming it's in parallel to a proper 50R load, it will present 27dB RL. That's not too concerning but measurable, and if you factor in edge effects and that there's a bunch of them on the board it might be noticeable.
But I just wanted to raise awareness of this for OP in case he wants to scale this up in frequency for his next design. As I mentioned the latest posted layout will probably work just fine from the routing impedance perspective.

[Bud]

. Besides, loss due to U4 (Bias-tee) is negligible?

Yes.

[x4ce]

Thanks for the suggestion.

Please do comment on this PCB layout which I have revised.

I have designed it for 0.6mm thickness PCB with 1.2mm track width. This track width is much wider and may cause clearance issues with other pads. I used another pad and aligned with components' pads so track keeps some clearance.

Bottom layer is solid ground and this is unfinished board.


Regards
Shahid