First time impedance matching ESP32-C3 with the TinyVNA-64

[okw]

It's my first time using the TinyVNA-64 and I have questions how to measure, read, and correct impedance (bluetooth).
I have attached the layout. Sorry for the poor naming, but layout is on bottom layer, so names are mirrored.

The layout shows the ESP32-C3, a series 0402 (#1) with two shunts (#2 / #3), an IPEX connector (A) for measurements, a SAW filter, then another series 0402 with two shunts (#5 / #6), IPEX (B) and then the antenna (from application notes SWRA117D).

First I started with no shunts (#2,#3,#5,#6), no series (#4), only a 0ohms in #1. I measured SWR with port 1 at point A (to get the impedance between MCU and saw filter) between 2.402-2.48GHz, and it gave me highest SWR 3.458 at 2.45GHz. So I figured this would be the best point to impedance match. See attached image(vna1). The "L/C match" function suggested four different combinations (if I understand the utility right?).
Since I had 2.7pF (for #1 - suggested 2.8pF) and 1pF (#3), I chose that combination. It only made things worse (see image vna2). I also tried to put the shunt in both #2, also with poor result. See vna3.

Before I move further to IPEX point B, I'm not sure I'm doing things correctly. Anyone care to help me with this?

For next revision of the layout: Is it even necessary to have the matching network between MCU and SAW filter? And between SAW and antenna, should I rather have used a T-network instead of PI?
(And I think I should have placed the shunts in line with RF, not a branch off of the series components.)

[tszaboo]

Why do you have a SAW filter?
About the matching. The layout needs to be improved a lot. All the pads for the components are a lot larger than your impedance controlled trace.
It is impedance controlled, right? You made it into a microstrip, CPW works much better for these sort of layouts. How many layers do you have?
The components marked 5, 6 and 2,3 needs to be on the stripline, or the microstrip. You cannot make a Y connection at this frequencies.
How do you calibrate the VNA? Is your calibration on the PCB? Do you work with an empty PCB or with the module on it? If you have the module on it, you need to cut it off when you measure the matching.

[okw]

Oh, I have a lot to learn I see

Why do you have a SAW filter?

I heard that the SAW filter (SAFFB2G45MA0F0A) cuts off quite effectively outsidd the bluetooth frequencies. Not sure if it adds any advantage, or just complicates things?

About the matching. The layout needs to be improved a lot. All the pads for the components are a lot larger than your impedance controlled trace.
It is impedance controlled, right? You made it into a microstrip, CPW works much better for these sort of layouts. How many layers do you have?
The components marked 5, 6 and 2,3 needs to be on the stripline, or the microstrip. You cannot make a Y connection at this frequencies.

I'll improve and add all suggestions on next layout.
2 layers.
Traces are not impedance controlled. Not sure how to do that. I'm using Eagle.

How do you calibrate the VNA? Is your calibration on the PCB? Do you work with an empty PCB or with the module on it? If you have the module on it, you need to cut it off when you measure the matching.

I calibrated the VNA directly on port 1.

I work with a fully assembled board, with the ESP-32 chip (not module).
I should probably have ordered a few empty PCBs.

[TheoB]

Put your intended matching components in a Smith chart https://www.will-kelsey.com/smith_chart. It shows you what to expect.

[Kean]

I would suggest you use a 4 layer stackup that allows you to ensure 50 ohm trace impedance.
You can skip controlled impedance to save cost, but at least do the calculations for trace width based on the stackup.
You also need to add a lot more ground vias around that whole RF area, and use at least one internal layer for a (reasonably) solid ground plane.

[Bud]

I calibrated the VNA directly on port 1.

Then the cable connecting the port to the board becomes part of the measured impedance, introducing loss and phase rotation, meaning you get wrong numbers.
You have to calibrate on the board end of the cable to calibrate it out. That may need some improvization.
Adult VNAs have a feature called Port Extensions, which moves calibration plane from the port to far end of the cable. I doubt this toy VNA has it.

[rteodor]

Adult VNAs have a feature called Port Extensions, which moves calibration plane from the port to far end of the cable. I doubt this toy VNA has it.

Never heard of "TinyVNA" but LiteVNA has port extension feature hidden under: Display >>> Scale >>> E-DELAY.

[tszaboo]

Oh, I have a lot to learn I see

Why do you have a SAW filter?

I heard that the SAW filter (SAFFB2G45MA0F0A) cuts off quite effectively outsidd the bluetooth frequencies. Not sure if it adds any advantage, or just complicates things?

About the matching. The layout needs to be improved a lot. All the pads for the components are a lot larger than your impedance controlled trace.
It is impedance controlled, right? You made it into a microstrip, CPW works much better for these sort of layouts. How many layers do you have?
The components marked 5, 6 and 2,3 needs to be on the stripline, or the microstrip. You cannot make a Y connection at this frequencies.

I'll improve and add all suggestions on next layout.
2 layers.
Traces are not impedance controlled. Not sure how to do that. I'm using Eagle.

How do you calibrate the VNA? Is your calibration on the PCB? Do you work with an empty PCB or with the module on it? If you have the module on it, you need to cut it off when you measure the matching.

I calibrated the VNA directly on port 1.

I work with a fully assembled board, with the ESP-32 chip (not module).
I should probably have ordered a few empty PCBs.

Indeed you do. It's a process, don't take it the wrong way.
For impedance control, you should get the Saturn PCB toolkit, using that will get you a very good ballpark.
You shouldn't start with a SAW filter. You are not going to need, typically it's needed if you have other transmitters simultaneously on the same PCB. These 2.4GHz ICs are designed to work in noisy environments.

Empty PCBs are very useful for matching. 4 layer board, while it's not impossible to design boards that work well with RF on 2 layer, it's extra effort, and usually not worth it unless you want to sell a lot of these.

I calibrated the VNA directly on port 1.

The calibration needs to happen at the end of the cable that's on the PCB.
Read this blog, it's the most approachable guide I've seen:
https://colinkarpfinger.com/blog/2010/the-dropouts-guide-to-antenna-design/

Only thing I usually do differently, I use UFL connector.

[okw]

For impedance control, you should get the Saturn PCB toolkit, using that will get you a very good ballpark.

I don't really get the impedance control calculators for microstrip, assuming that's what I have?
It gives me ~110mils track width, which seems tremendously wide. Could that be right? Then I need some teardrop going into the ESP32, every matching components and the trace antenna?

(I'll stick with 2 layer, as it might be some quantity, and 1.6 thickness as I need the sturdiness.)

[tszaboo]

For impedance control, you should get the Saturn PCB toolkit, using that will get you a very good ballpark.

I don't really get the impedance control calculators for microstrip, assuming that's what I have?
It gives me ~110mils track width, which seems tremendously wide. Could that be right? Then I need some teardrop going into the ESP32, every matching components and the trace antenna?

(I'll stick with 2 layer, as it might be some quantity, and 1.6 thickness as I need the sturdiness.)

That can be correct for two layer boards. There is a reason why typically 4+ layer boards are used for RF. Look at the Raspberry pi pico. They really insisted on impedance control, and 2 layer board, and they ended up with those really wide traces for the 90 Ohm USB, with the reduced height board.

[okw]

For impedance control, you should get the Saturn PCB toolkit, using that will get you a very good ballpark.

I don't really get the impedance control calculators for microstrip, assuming that's what I have?
It gives me ~110mils track width, which seems tremendously wide. Could that be right? Then I need some teardrop going into the ESP32, every matching components and the trace antenna?

(I'll stick with 2 layer, as it might be some quantity, and 1.6 thickness as I need the sturdiness.)

That can be correct for two layer boards. There is a reason why typically 4+ layer boards are used for RF. Look at the Raspberry pi pico. They really insisted on impedance control, and 2 layer board, and they ended up with those really wide traces for the 90 Ohm USB, with the reduced height board.

I also have a crystal problem which is taken care of in the next version of the board. The crystal was waaay out of spec which made the BT frequency far off. With 180pF load capacitors I forced the BT frequency to "only" be about +75 to +85ppm off (ESP32 design guidelines recommends less than +/-10ppm). If I tried to force it closer (with higher cap values) the MCU wouldn't start. Evert time I increase the load capacitors, the signal amplitude would drop. So I suspect a might higher TX power, and a +/-10ppm center frequency when I get a good crystal with normally sized caps (7-20pF).
At the moment (with the above problems) I still enjoy 9-10 meters distance (with a few thin walls between), without any data corruption.
Besides range, what would be the effect of having narrower feedline than the 110mils? For example  40-50mils.

[rteodor]

Correct me if I'm wrong but controlled impedance should not matter if the tracks are short, under 10% of the wavelength. 3e8 / 2.45e9 * 0.66 * 0.1 = cca. 8mm.

The small appendices like the ground track under components 5 and 6 might have enough inductance to upset the matching network.

[okw]

Correct me if I'm wrong but controlled impedance should not matter if the tracks are short, under 10% of the wavelength. 3e8 / 2.45e9 * 0.66 * 0.1 = cca. 8mm.

The small appendices like the ground track under components 5 and 6 might have enough inductance to upset the matching network.

I like the sound of that But what is the 0.66 factor you use?

[rteodor]

But what is the 0.66 factor you use?

That would be a very crude approximation of velocity factor: 0.66 = 1/sqrt(4.6/2) where 4.6/2 is the relative dielectric permitivity of PCB material (from the Saturn screenshot above) divided by 2 because half of the electric field is traveling in PCB and the other in air.

[tszaboo]

Correct me if I'm wrong but controlled impedance should not matter if the tracks are short, under 10% of the wavelength. 3e8 / 2.45e9 * 0.66 * 0.1 = cca. 8mm.

The small appendices like the ground track under components 5 and 6 might have enough inductance to upset the matching network.

This rule gets applied wrong every single time. Yes the impedance doesn't matter that much for short traces, so you can treat it more like a lumped element. So your very thin trace gets turned into an inductor. Maybe you need an inductor in your transmission line, maybe it's the wrong part. But you will be unable to measure it with a VNA because you cannot connect it properly, you painted yourself into a corner with that inductor, and your matching circuit is still messed up with wrong footprints and long traces.
Just impedance control that trace, and all this issues disappear.
Don't believe me? Measure it out or calculate it in a free calculator like QUCS, don't just parrot it.

[rteodor]

Correct me if I'm wrong but controlled impedance should not matter if the tracks are short, under 10% of the wavelength. 3e8 / 2.45e9 * 0.66 * 0.1 = cca. 8mm.

The small appendices like the ground track under components 5 and 6 might have enough inductance to upset the matching network.

This rule gets applied wrong every single time. Yes the impedance doesn't matter that much for short traces, so you can treat it more like a lumped element. So your very thin trace gets turned into an inductor. Maybe you need an inductor in your transmission line, maybe it's the wrong part. But you will be unable to measure it with a VNA because you cannot connect it properly, you painted yourself into a corner with that inductor, and your matching circuit is still messed up with wrong footprints and long traces.
Just impedance control that trace, and all this issues disappear.
Don't believe me? Measure it out or calculate it in a free calculator like QUCS, don't just parrot it.

Yes measuring one track alone might be hard but measuring the whole circuit is not. And observing the effects of changing a component one could determine the parasitic inductances.
But yup I agree, it would be tedious.

I'll try it sometime as I need to refresh my Smith chart navigation skill.

[okw]

Would coplanar waveguide be a good choice for this?
If feedline is 24.87mils and 3.5mils gap to ground fill, or 33.5mils / 5mils, it would give me 50ohms impedance.

However, antenna (exact SWRA117 copy) is 19.685mils wide. If I want to "match" the width i need a 2.7mils gap, and it's less than the PCB house capabilities.

Should I match the 19.685mil (and 3.5mil ground fill gap), or just go with any of the calculated ones above? Which is best?

Should I make a teardrop out of the MCU and into the antenna?

[tszaboo]

Coplanar waveguide works very well. If brings the ground to the top, is it's easier to place the matching circuit. And the tracks are thinner

[okw]

Coplanar waveguide works very well. If brings the ground to the top, is it's easier to place the matching circuit. And the tracks are thinner

Do I still use a complete ground copper fill on the bottom layer under the feedline (in addition to the the top layer ground fill around the feedline)?
And do I put via stitching along the feedline on the ground area? How far should I place them from the ground outer line and what spacing between them?

[tszaboo]

Coplanar waveguide works very well. If brings the ground to the top, is it's easier to place the matching circuit. And the tracks are thinner

Do I still use a complete ground copper fill on the bottom layer under the feedline (in addition to the the top layer ground fill around the feedline)?
And do I put via stitching along the feedline on the ground area? How far should I place them from the ground outer line and what spacing between them?

Yes, ground fill on the layer just below (or bottom on 2L) and no other traces there. I think the suggestion is maximum of 1/10th of wavelength for the vias. Altium has some blog posts with simulations about this as I recall. I typically place them around as close as they get, they are free after all.

[aninstone]

Nice work