GaN class E/F_odd HF transmitter: logic-gate drive, 14W out, 90+% efficiency

[mark03]

I just finished a fun little project, a test board for a "class E/F_odd" transmitter using EPC2037 Gallium Nitride active devices.  My longer-term goal is to experiment with polar modulation as discussed in this thread:
https://www.eevblog.com/forum/projects/smps-design-questions-for-rf-amp-eer-kahn-technique/
but the immediate objective was to verify the SPICE simulations and practice soldering the bare-die GaN FET packages.

(See http://k6jca.blogspot.com/2011/01/80-meter-class-ef-rf-amplifier.html and his preceding blog entries for a discussion of the class E/F_odd topology, with references at the end of the page.)

Schematic:



I laid out a four-layer board and ordered from OSH Park.  Here is the assembled PCB with a 50-ohm dummy load at the output; the size is only about 10 cm^2:



I guesstimated the air coil size and number of turns from an online calculator.  It is a quasi bifilar winding in an effort to keep the coupling coefficient as high as possible.  But I must have been pretty far off, because the best operating frequency was 10.8 MHz, not the intended 13.56 MHz.  Not a big deal for the purposes of this experiment.

The GaN FETs are ridiculously small, 0.9 x 0.9 mm with 0.4 mm ball pitch (2x2).  I burned through some parts during the learning curve, but at $1.50 each, that was not so painful.  The winning formula was a *thin* layer of tacky flux (Chip Quik SMD291NL), several minutes on the hot plate to equalize temperatures at ~ 150 C, then 260 C hot air at very close range for much longer than I thought advisable.  I think my problem was failing to use thermal reliefs on the pads; the copper planes were sucking heat out as fast as I could apply it.  One of the FETs looks good but the other is badly tilted, although the board seems to work.

Close-up of the GaN FETs and "gate drivers" (single UHS logic gates).  The FETs are about as wide as the blue-colored 0603 passives:



I ran the drain supply all the way up to 15V, with 0.96A DC input current, yielding 14W RF output.  Not bad for active devices barely visible to the naked eye, and no heat sink!  (EPC says R(ja) ~ 100C/W.)  I wish I had better efficiency numbers, but I was measuring rms load voltage with my Rigol scope, which isn't terribly accurate:  I was calculating drain efficiency ~ 96% or even higher, awesome... until I started getting some "over unity" efficiencies at low power   Oops.

Odd-order harmonic output seems to match the LTSpice simulation, but there was a second-harmonic component roughly equal in amplitude to the third harmonic.  I am guessing this points to the need for a phase delay/advance mechanism between the FET drive signals because the FETs don't have identical characteristics.  Or maybe it's due to imbalance in my coil winding?

The next step is to dig into the FPGA side of the project, to see how I can generate a phase-modulated carrier square wave.  I expect to try something like the delay lines used in TDCs (time to digital converters), as the phase-modulation task is essentially a "digital to time" converter.

[T3sl4co1l]

More likely in the gates.  Both guarantee 0.5 to 4.5ns (at 5V), which is the broad side of a barn.

Likely, in practice, one has an extra inverter gate delay inside, and the other doesn't, and that accounts for the difference.

You could RC delay one or the other, just add some footprints for components and figure out which one needs a zero-ohm jumper in that position, and which one needs, say, 47 ohms and 10pF or thereabouts.

Have any problems with PCB fab?  The tiny pad-to-pad clearances always bothered me about those things, as well as the impossibility of solder mask between pads (at least, without going to a more expensive LDI process).

Did you measure die temperature?  You want to use a very fine thermocouple, and a dab of thermal paste, to probe that.  Alternately, some polyimide tape (to ensure high emissivity) and a thermal cam, if you have one with a zoom lens to actually resolve the component in question!

Tim

[mark03]

Ah yes, the extra delay in the noninverting gate had occurred to me earlier, but for some reason I'd forgotten.  You're probably right.

The copper tolerances on OSH Park's four-layer boards are pretty good---5/5 trace/space---but I was concerned about the solder-mask registration.  EPC insists on SMD (solder-mask-defined) pads; interestingly I found other bare-die parts where the opposite recommendation was made!  But who am I to argue?  So I ended up expanding the copper pads about as far as I could (around 6 mil spacing IIRC); at the same time I used a fairly small aperture on the solder mask, reasoning that this combination would permit a larger registration error without ruining the footprint, and at the same time, increase the standoff height a little bit to compensate for using flux only, no paste.  Here's the footprint in Kicad with 0.05-mm grid lines and the solder mask layer in purple:



BTW I was surprised at the aspect ratio of the part.  It's almost a cube!  Are silicon wafers normally that thick (~0.5 mm)?

I don't have a thermal camera or tiny thermocouples, so I didn't measure the die temperature.  At 14W output I set it up next to a box fan, but that was mainly because I had a wimpy heatsink on the 50-ohm load resistor.  In theory you *can* heatsink the FETs and go quite a bit higher.  Vds at 50W output is still ~ 20V shy of the limit, although you hit the max drain current a bit lower than that, maybe 30-40W.

Somewhat more embarrassingly, I have not put a scope on the drain waveform yet; I only tuned the input (at low drain voltage) for minimum harmonics in the output.  I still need to dig into the Rigol parts bag and see if they supplied a probe-tip clip-on thingies, then scrape off some soldermask, because I forgot to leave myself test points.

[langwadt]

Ah yes, the extra delay in the noninverting gate had occurred to me earlier, but for some reason I'd forgotten.  You're probably right.

That's why the article you linked to used XOR gates, inverting and non-inverting delay should be similar and being on
the same die track reasonably well

[JohnG]

I would not recommend using thermal vias. The fact that they ease soldering means they are worse at conducting heat out of the FET. Good for soldering, but bad for operation. The more copper, the better, at least from a thermal point of view.

An oven helps tremendously, although I have successfully reworked FETs in a manner similar to what you describe. When you use the hot plate, I would make sure the PCB is getting to 150C, and a few degrees hotter can help. For an oven, I actually use the Controleo3 with good results.

John