GCPW with Via Stitching

[Randy222]

Is there a free design tool that provides optimal signal trace width, spacing, and via stitching or fencing (sizing/spacing/location) for given board type/weight, length, frequency, and desired impedance.

GCPW is well documented and available in many tools, but adding via stitching/fencing is extra math which impacts impedance if other parameters are not adjusted correctly, and I don't find tools that include via stitching or fencing.

I ran across this Python simulator, very cool, but I want tool to help provide the base numbers making it faster to get to ordering up boards.

https://www.flexcompute.com/tidy3d/examples/notebooks/GroundedCPWViaFence/

[ejeffrey]

I haven't found that to be necessary.  When I have used gcpw, I try to place the ground vias far enough away that they don't significantly affect impedance.  I just make a hand waving estimate. If I really care I always do a process characterization test structure anyway, so I correct any remaining error that way.

If you really want to simulate the exact structure, you need a field solver like hfss.

The best middle ground is atlc2.  This can't simulate full 3d structures but can simulate an arbitrary uniform cross section transmission line.   If you simulate a gcpw with a solid wall instead of shielding vias you can bound the impedance change quite closely

[Randy222]

The flexcompute python code does a very good job in simulation for controlling the undesirable modes, and we can see relationships between the parameters they use, it however does not evaluate the impedance after adding the vias.

Altair also gives a decent general guideline for vias, but they too do not describe the impact vias have on impedance.
https://help.altair.com/feko/topics/feko/user_guide/appendix/how_tos/feed_cpw/construct_cpw_feko_t.htm

I did read elsewhere that the spread distance should be near 1/2 lambda (1/4 wave to left of center signal track, and 1/4 wave to right of center signal track). This after doing std GCPW design.

In some other online discussions a user found discrepancy of 4ohms due to vias because they introduce some reactance.

If it's not a tool that enumerates optimal values for the GCPW design, then perhaps a tool where we can input values manually and the tool calculates impedance account for the reactance from vias.


All that said, in std GCPW the signal plane side ground fills need to be connected to the ground plane side, so it needs vias somewhere, or the ports(in out ports) need to attach it's ground to all the ground fills. I assume adding via fencing enhances this setup, yet the via reactance needs to be accounted for.

Using just some general rules (as defined by many online sources), for fencing, distance from trace edge should be 2-3x the pour gap "S". Via spacing around 1/8 to 1/10 lambda of highest frequency in application.

So design std GCPW, take the side pour gap and x2.5 that as value "d", then center of via shall be placed "d" away from the edge of the signal trace. That's good, but the vias still impact the impedance derived from std GCPW design, which is what I am trying to obtain, so that something like pour gap or trace width can be adjusted to account for the vias.

[ftg]

...
I did read elsewhere that the spread distance should be near 1/2 lambda (1/4 wave to left of center signal track, and 1/4 wave to right of center signal track). This after doing std GCPW design.
...

Is this for the highest frequency component or something like that?
Because the numbers you'd get for this even on 2.4GHz or 5GHz are rather huge.

[Randy222]

Yeah, 1/2 wave for under like 40G is a bit large.
I have all the general rules for vias, but I am after knowing how placement/size/spacing affects impedance.

[EggertEnjoyer123]

Here is an interesting resource:
https://mpd.southwestmicrowave.com/wp-content/uploads/2018/07/Optimizing-Test-Boards-for-50-GHz-End-Launch-Connectors.pdf

The summary is that you need to place the vias as close to the edge of the CPW as possible, and the spacing between the vias has to be as small as possible. The relevant information is on pages 17 to 19 (15-17 if you rely on the numbers on the bottom right corner).

You can probably build a model in FreeCAD and use OpenEMS to arrive at the correct impedance. You can get the impedance by doing the inverse FFT on the S11 data to get the time domain response. I don't know of any calculators for it though, so you might have to simulate it. It should only take a few minutes though (to run the simulation). I'm lazy though and I just assume that the impedance is the still same with vias. Might have to actually simulate it someday to make sure.

[Randy222]

Very good PDF, so I read more.

I have SonnetLite, but I am not well versed in Sonnet. Will try some simulations.

[Marsupilami]

Check out RF 2D Field Solver by the LibreVNA guy.
I don't know how accurate it is, but if nothing else, you can get a good feel about relative changes. It is really educational observing the field distribution.

My two cents is go hard or go home. Via fence as tight as fab rules allow. If I have to make sure there isn't anything leaking out in the dielectric then double or triple the rows with an offset.
There isn't anything useful about a via fence that doesn't act like a solid wall. Now if you're designing high-performance mmWave radar, then my condolences and disregard everything here, but otherwise it is not that big of a deal.

As for impedance, this is where the structure geometry comes in, and you should play with the field solver to see. If your dielectric height is significant with a wide trace and narrow gap you will see an effect as the gnd surface of the via is relatively close to the trace to contribute to capacitance.
If the structure is "flat" and wide, the vias are not going to change much. Also keep in mind, that for most sane fab technologies you will need an annular ring around your via, which will set the via wall in from the coplanar gnd edge. This slight offset is often enough for the bulk of the field lines in the dielectric to connect from the coplanar gnd edge instead from the via wall, thus making the via irrelevant from the impedance perspective.

HTH   

[Randy222]

Good info thus far.

What I find a bit baffling is that GCPW usually has the upper gnd tracks attached to the lower ground plane, usually with vias somewhere.

And then I wonder about why vias at all if the feed port is like an SMA pcb edge mount where the ground lugs connect to the top gnd tracks and the bottom gnd plane. Are vias even needed in this setup?

The SW Microwave PDF that shows lots of vias seems to be approaching the stripline design (electrically). With so many vias I wonder if a plated slot would accomplish the same thing? Their many-via GCPW does appear it's the vias that are connecting the top tracks to the lower gnd plane.

[ejeffrey]

You need the ground stitching vias to avoid launching to antenna modes of the upper split ground plane and waveguide modes of the substrate, as well as reducing crosstalk to nearby sognals.  For the intended transmission line mode there should be very little current flowing in these vias, which is why they don't have a tremendous effect on the impedance.  For the geometries I have simulated it's maybe a few percent.

In principle if you launch perfectly and have a perfectly uniform, straight, symmetrical transmission line you don't need ground vias at all.  The transmission line mode is a "normal mode" and ideally perfectly decoupled from all the other modes of the system.

In reality small imperfections in any of the above can cause leakage to the undesired modes.  Periodic ground vias short the undesired modes out, keeping all three ground planes at the same rf potential, at least at "low" frequency. 

How much of an impact it makes depends on their location and on the type of GCPW.  It's possible to make a GCPW with a thin substrate and wide traces which is closer to a microstrip, or with a thick substrate and narrow traces which is closer to a pure CPW.  At the microstrip end of the spectrum most of the current flows in the bottom ground plane and the ground vias are automatically far from the bulk of the fields and have very little effect.  In the CPW limit most of the current flows in the upper ground planes and there is more potential for the vias to affect the impedance, depending on how close they are.

[Randy222]

If the ports on each end of line are grounded to the ground tracks and bottom plane, what then do vias do connecting gnd to gnd. Will Rf (40GHz, 100GHz) start to skin on only the upper tracks and form potential diffs between gnd tracks and gnd plane? I guess I need to investigate this further.

[Randy222]

Even chatGPT seems to just reiterate what it can find on internet, vs actually being able to do the calculations with and without vias.

I plan to run my own testing by building a few test setups.

[ejeffrey]

Even chatGPT seems to just reiterate what it can find on internet, vs actually being able to do the calculations with and without vias.

Yes, you have correctly determined how LLMs work...

[Randy222]

Even chatGPT seems to just reiterate what it can find on internet, vs actually being able to do the calculations with and without vias.

Yes, you have correctly determined how LLMs work...

Correction. I know how they work. I was asking in a chatGPT Business subscription, you get more "LLM" there. LOL.

I have some good general design parameters to work with, i'll toss up a design to look at. It's not Rogers board, just plain 'ol FR4, so an obvious limitation.

This one is tuned for 1GHz 1/2wave port to port. Trace and spacing chosen to match edge launch SMA closely. Probably order some with vias and some without.

[tggzzz]

Even chatGPT seems to just reiterate what it can find on internet, vs actually being able to do the calculations with and without vias.

If you think LLMs can predictably/reliably do more, then you don't understand the basic principles inside LLMs.

Yes, ejeffrey is right.

[Randy222]

Most LLM's know more than most people, so they do help.
I "know a lot about Rf" and other things, so I (and you / others) can spot the issues.

I was able to get chatGPT to run 2D calculations just by asking to build a GCPW with some basic info (size, board type, frequency, impedance, feed port type), even generated some Python, but it fell short of doing 3D simulations, but would just recommend other tools like Sonnet Lite.

Useful to a limited extent. For the newb it can help get the ball rolling that 1mm, the rest is homework.

What I find interesting, is SW Microwave edge launch connectors say soldering the pin to board is optional.

[tggzzz]

Most LLM's know more than most people, so they do help.

That's why it isn't unreasonable to regard LLMs as the revenge of the unskilled.

They might help, until they don't. And the consequences of the "don't" can be far more significant than the "do".

I "know a lot about Rf" and other things, so I (and you / others) can spot the issues.

It is typical that people who don't know the subject (e.g. managers, politicians) rate LLMs far higher than those who do know the subject. That doesn't mean the issues are unimportant; frequently they are subtle killers.

Now, if you had to assess a product/proposal/company will that be easier or more difficult if the other party had used an LLM.

Remember the standard complaint about consultancies: "they bid the A-team and fielded the B-team". LLMs mean even that A-team isn't needed. Do you think the final outcome will be better or worse?

[Randy222]

I agree, those who think the LLM's are great wonders, are probably not well educated. Hence the issue we are all about to face. Most dangerous in things like medical, some newb "PA" who uses their business subscription to some LLM when the sneeze has them baffled.