Did this get cleared up? It seemed like an interesting idea with maybe a simple solution. Been thinking about it for a while, no simple solution I could see. But I've modelled what looks like a complex solution in ltspice which IN THEORY could be implemented with 2 x 74HC74 dual flip-flops and 1 X 74HC00 quad nand gate. Which is not a big investment. I say in theory because I'm not sure if gate delays will introduce glitches.
I'm not sure how to pass it on. I will attach the ltspice diagram and the output waveform.
An explanation. V1 is a 1MHz pulse train (I don't know the characteristics of the generic ltspice digital models so I chose something slower than 10MHz). V2 is an emulated 1pps, but much faster so several extended pulses appear in a short time. V5 is a logic 1. Used by the generic AND (used here as a NAND) gate which has 5 inputs, only two are used so the rest need setting to logic 1.
When no 1pps is being processed, the pulse signal path is through nand A3 where it gets inverted, then through nand A4, which inverts it again. Only one pulse out of 2 is required, Flip-flop D1 manages this as its output is half the input, it enables A3 via A2 every second pulse.
When a 1pps is detected, the first part of the output pulse is just passing the input pulse. D1 Q goes high, all inputs of A2 are high including the input from V1, meaning A2 is acting as an inverter of the signal from V1 and outputs a low. D4 has not yet received the information about the 1pps so its Qbar is high, all inputs of A3 are high except the input from A2, so A3 outputs a high (the original pulse).
The 1pps detection is done by D2 - it is set by the rising edge of V3. To synchronise this with the pulse train, its value is passed to D3 on a rising pulse from D1. D3 latches D2, D2 output is no longer required so D3 resets D2. A1 is used as an inverter so that D4 latches D3 on a falling edge of the original input pulse. Having latched the D3 value, it resets D3. The D4 Qbar value, which most of the time is high, goes low. It causes A3 to putput a high regardless of the value from A2, until the next falling edge of the input. This extends the output by one cycle of the input.