Hello EEVBLOG community,
I've been messing around with my RF microstrip traces for a while now in an attempt to achieve proper signal quality and I keep coming up short with poor signal quality with every design iteration thus far. I'm beginning to wonder if I have something simple wrong that I am not aware of (some design rule I'm probably overlooking or haven't found so far).
Essentially, the signal chain I have is:
Flat patch 4G LTE antenna, coax cable to u.fl female connector (50Ω) -> u.fl SMD male connector (50Ω) -> Microstrip line RF trace (50Ω, according to JLCPCB impedance controlled design) -> MAIN_ANT pin on a SIM7600E RF module.
I have a strong feeling that my issues lie within my PCB trace layout. I've done a fair bit of experimentation with matching networks (using information gathered using a NanoVNA), various trace widths (as a sanity check test), via placements for grounding, trace lengths (shortest possible) and nothing seems to have done the trick so far.
For reference, I'm including some diagrams of my current trace design (JLCPCB 7628 stack-up
https://cart.jlcpcb.com/impedance 4 layer board, 1.6mm PCB thickness, 11.55 mil trace width, 7.1 mil conductor height, FR-4 dielectric).
top_L1.png: Shows the top layer of the PCB, centered around the 3 pin U.FL SMD connector with RF trace going to the MAIN_ANT pin of the SIM7600E.
ground_L2.png: Shows the 2nd layer of the PCB (a full uninterrupted ground pour for the RF microstrip), centered around the 3 pin U.FL SMD connector.
I've done some due diligence (digging around on the EEVblog forums) and found out that the U.FL connector actually has a keep-out layer around the signal pad (which I haven't tried including yet), and some others were also recommending a 3x trace width buffer between the RF trace and the top layer ground pour on either side.
Besides these solutions, is there anything else I'm missing? I'm new to designing with RF and would love some feedback
.