Author Topic: Idea for improving LTDZ Spectrum Analyzer & Tracking Generator 35MHz-4.4GHz  (Read 24281 times)

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Offline KalvinTopic starter

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I am interested in the LTDZ 35MHz - 4.4GHz spectrum analyzer & tracking generator containing STM32F103 processor for a hobby use (amateur radio). After watching some videos and reading VMA's satellite blog, it is obvious that there are some problems and shortcomings with the existing design. For example, the default RBW is about 120 kHz, and it cannot be changed dynamically. For a general RF filter measurement and SSB spectrum analysis, this wide RBW makes this otherwise very nice instrument almost useless.

Looking at the schematics, the output of the RX mixer is fed through a 120 kHz low pass filter (read: RBW-filter) into input of a AD8307 LOG amplifier/detector. The output of the LOG detector is then fed to STM32F103's ADC input.

Since the STM32F103 has a 12-bit ADC which can run up to 1Msps, why not drop the AD8307 altogether, feed the 120 kHz filter directly into the ADC input, and make the STM32F103 do the required math and DSP. The ADC would give theoretically 12*6dB = 72dB of dynamic range, which is quite similar to AD8307 anyway. Then the STM32F103 could implement adjustable RBW, perform even FFT if needed. At the same time one can even obtain 1 - 3 bits of conversion gain (6dB - 18dB) with narrower RBW for improved dynamic range (if the noise floor is practically low enough). There are some alternative firmwares available which could be used as a starting point for this modification.

What do you think? Do you see any reasons why this scheme would not work?

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Project at Github: https://github.com/kalvin2021/ltdz-dsp

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Here are some pointers to books related this subject:

Freely available ebook "The Scientist & Engineer's Guide to Digital Signal Processing, 1999" by Analog Devices:
https://www.analog.com/en/education/education-library/scientist_engineers_guide.html

Freely available ebook "Software-Defined Radio for Engineers, 2018" by Analog Devices:
https://www.analog.com/en/education/education-library/software-defined-radio-for-engineers.html

Practical introductory book about digital signal processing without too complex mathematics (pun intended):
Lyons: Understanding Digital Signal Processing, 3rd Edition

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PCB:
1220127-0

Schematics:
1220129-1

Edit: Added the books, PCB and schematics.
« Last Edit: June 09, 2021, 09:08:10 am by Kalvin »
 

Offline radiolistener

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why not drop the AD8307 altogether, feed the 120 kHz filter directly into the ADC input, and make the STM32F103 do the required math and DSP

Using digital filter slows down STM32 and don't provide any benefit. There is no need for configurable bandwidth. It just make sweep very slow and low dynamic range.

And AD8307 is logarithmic amplifier with 92 dB dynamic range, so it allows to increase dynamic range by using logarithmic scale. If you remove it, you will get linear scale and bad dynamic range.

If you're not satisfied with software results, you can try my version NWTSHARP-LTDZ, it supports LTDZ and NWT7 devices and use better calibration algorithm, also you can see RAW ADC charts. Just select COM port, press Connect and then Sweep.

My LTDZ instance dynamic range is 50 dB. And it's limited by RF frontend design. In order to get better, it needs a new PCB. There is already exist exactly the same hardware with better PCB layout and shielding, but it cost much more.
« Last Edit: May 10, 2021, 08:27:57 pm by radiolistener »
 

Offline KalvinTopic starter

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why not drop the AD8307 altogether, feed the 120 kHz filter directly into the ADC input, and make the STM32F103 do the required math and DSP

Using digital filter slows down STM32 and don't provide any benefit. There is no need for configurable bandwidth. It just make sweep very slow and low dynamic range.

For your satellite spectrum observation purposes the 120 kHz RBW might be ok, but for applications that require more detailed spectral analysis, this 120 kHz RBW is way too wide, and makes the board basically useless.

If one wants to obtain narrower RBW with more spectral details, it is necessary to reduce the RBW from 120 KHz down to 1 KHz or even less, depending of the spectral details one wants to see. Yes, this will slow down the sweep rate, but in applications that requires more spectral details like tuning a narrowband filter or investigating narrow SSB spectrum, this needs to be done either in analog domain (AD8307) or in digital domain (using numerical DSP-algorithms).

Bypassing the AD8307 LOG-detector altogether, feeding the output of the 120 kHz lowpass-filter directly into STM32F103 ADC input, sampling the signal with up to 1Ms/s, and performing the final RBW-filtering and LOG-detector in MCU with some math/DSP, one can select narrow RBW-filter dynamically, and gain some extra dynamic range due to processing gain.

For more advanced spectrum analysis, one can even implement FFT for computing the spectral components, and one can get very narrow RBW and good spectral resolution without slowing down the sweep rate. That is something that really cannot be done with AD8307 if you reduce the RBW for improved spectral resolution.

And AD8307 is logarithmic amplifier with 92 dB dynamic range, so it allows to increase dynamic range by using logarithmic scale. If you remove it, you will get linear scale and bad dynamic range.
<snip>
My LTDZ instance dynamic range is 50 dB. And it's limited by RF frontend design. In order to get better, it needs a new PCB. There is already exist exactly the same hardware with better PCB layout and shielding, but it cost much more.

This is partially true. By taking advantage of the processing gain you can compensate the "seemingly lost" dynamic range of 72dB of a 12-bit ADC when using narrower RBW filters. With the original 120 kHz RBW, you can still get extra dynamic range by oversampling and averaging, but this will obviously slow down the scanning rate as more samples are needed.

As you have stated, the actual obtainable dynamic range may be only 50 dB for a given board/design. Even if AD8307 is technically able to provide 92 dB of dynamic range, in practice you will get much less than that due to the noise floor of the board. In that sense the 12-bit ADC with 72dB of dynamic range is sufficient, and the STM31F103 is able to compute the LOG-detector with 72dB dynamic range in software without any problems.
 
Some newer boards are said to be able to give up to 70 dB of dynamic range, so the 12-bit ADC is still sufficient for the LOG-detector, and AD8307 does not provide any real benefits. Of course, the signal level needs to be set correctly so that the full dynamic range of ADC can be utilized. With the processing gain obtainable using the narrower RBW and/or oversampling/averaging, one can compensate lost dynamic range to some extent, even if the signal level is not perfect.
« Last Edit: May 11, 2021, 07:14:40 am by Kalvin »
 

Online Bicurico

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If you want to use such small RBW you will either need a professional class spectrum analyser like the Siglent SSA3021X/X-P/-RT/SVA series or you might try your luck with SDR alike devices like the HackRF one or Adalm Pluto (using Satsagen).

I just tested the Arinst SSA-R2 TG and it is a much better performing device than the SMA/NWT/D6/LTDZ devices. However, it uses a fixed RBW of 200 kHz (https://vma-satellite.blogspot.com/2021/05/arinst-ssa-r2tg-one-of-themost-frequent.html).

The last cheap option would be a TinySA. At 50 Euro it is very cheap, but in EU you will probably end up getting a fake clone, unless you buy at AliExpress from Zeenko Store and handle customs yourself.

It seems to have a configurable RBW, but it is otherwise limited in terms of frequency range.

At the end of the day, it all depends on what exactly you want to do.

Regards,
Vitor

Offline KalvinTopic starter

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I agree that the phase noise may become an issue with smaller RBWs when using AD4351. Unfortunately I do not have any measurement data for the phase noise for these chinese boards. Fortunately there is some measurement data available, giving -60 ... -70 dBc@1 kHz for AD4351: https://www.eevblog.com/forum/rf-microwave/adf4351-simple-you-would-think/msg2514417/#msg2514417

I do have a genuine TinySA and Adalm Pluto, but wanted to take a look at these inexpensive AD4351-based spectrum analyzers / tracking generator boards, and see how their performance could be improved so that these simple and inexpensive boards would be better suited for a typical radio amateur-related measurements (spectrum analysis, filter measurements, signal generator) from the upper HF frequency range, up to UHF frequencies even beyond 1 GHz. Adding a cheap SWR bridge would create a decent and very inexpensive antenna analyzer for frequencies above 35 MHz, for example.
 

Offline radiolistener

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You can improve input SWR by removing 51 Ω on the input. With that mod input impedance will be more close to 50 Ω, because by default it has about 30 Ω input impedance. But it will leads to overload for LTDZ output, you're needs to use attenuator.

Regarding to the filter bandwidth, you can modify filter circuit and get more narrow bandwidth. But narrow bandwidth leads to gaps for a large frequency step. Since max point count is 9999, you will get:
- sweep from 35 MHz to 1 GHz = 96.5 kHz step
- sweep from 35 MHz to 2 GHz = 196.5 kHz step.
- sweep from 35 MHz to 4 GHz = 396.5 kHz step

So, 120 kHz bandwidth is good for a usual sweep from 35 MHz to 1.23 GHz
 

Offline KalvinTopic starter

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You can improve input SWR by removing 51 Ω on the input. With that mod input impedance will be more close to 50 Ω, because by default it has about 30 Ω input impedance. But it will leads to overload for LTDZ output, you're needs to use attenuator.

Regarding to the filter bandwidth, you can modify filter circuit and get more narrow bandwidth. But narrow bandwidth leads to gaps for a large frequency step. Since max point count is 9999, you will get:
- sweep from 35 MHz to 1 GHz = 96.5 kHz step
- sweep from 35 MHz to 2 GHz = 196.5 kHz step.
- sweep from 35 MHz to 4 GHz = 396.5 kHz step

So, 120 kHz bandwidth is good for a usual sweep from 35 MHz to 1.23 GHz

Thanks, I will investigate the input resistor/impedance as soon as I will receive my board. I will use SMA-attenuator(s) as needed, which will also help with the SWR.

I would not like to modify the board so that the filter will become fixed (again), because the whole idea is to modify the firmware so that it would be possible to select the RBW dynamically without further hardware modifications. So far the only modification in the hardware would be to bypass the AD8307 LOG-detector, and let the STM32F103 do the filtering, LOG-detector and possibly some further signal processing like FFT. It seems that there are some unused MCU ADC-input pins available, so it might be even possible to keep the AD8307 operational, and add a wire from filter output to the MCU ADC-input pin for the dynamically selectable RBW feature. Let's see what is possible/useful with this hardware.
 

Offline gf

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The 0Hz IF is not really suitable for channelizing the IF band into narrower bands (e.g. via FFT), since the input signal bands [fLO-BW...fLO] and [fLO...fLO+BW] do alias in the down-mixed (real-valued) IF signal, and the original upper and lower bands cannot be separated any more. Upper/lower band separation were not a problem if the IF signal were complex (I/Q), but I guess it is not a quadrature mixer.

For the original use case, this aliasing does not matter since only the total power of upper and lower band together -- i.e. [fLO-BW...fLO+BW] -- is calculated. But for further channelizing it does matter.

Still you have the option, of course, to apply a digital lowpass with an even lower cutoff frequency to the pre-filtered IF signal.

[ BTW, if the lowpass filter has (single-sided) bandwidth of BW, then the corresponding bandpass bandwidth is actually 2*BW, i.e. RBW is even wider. ]

EDIT:
If the frequency response of the analog lowpass filter (on this web page) is correct, then digitizing is challenging, too. If I extrapolate the filter's transition band to -100dB below peak, then I get a required Nyquist frequency of about 4MHz, requiring a sampling rate of 8MSa/a. If only the (say) 0...300kHz band is eventually evaluated in the digital domain, then one could accept some foldback and allow a lower Nyquist frequency of (4000+300)/2=2150kHz. Required sampling rate were still 4.3MSa/s then. Depends of course on the desired image rejection (I assumed 100dB).
« Last Edit: May 12, 2021, 02:38:23 pm by gf »
 

Offline KalvinTopic starter

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The 0Hz IF is not really suitable for channelizing the IF band into narrower bands (e.g. via FFT), since the input signal bands [fLO-BW...fLO] and [fLO...fLO+BW] do alias in the down-mixed (real-valued) IF signal, and the original upper and lower bands cannot be separated any more. Upper/lower band separation were not a problem if the IF signal were complex (I/Q), but I guess it is not a quadrature mixer.

For the original use case, this aliasing does not matter since only the total power of upper and lower band together -- i.e. [fLO-BW...fLO+BW] -- is calculated. But for further channelizing it does matter.

Still you have the option, of course, to apply a digital lowpass with an even lower cutoff frequency to the pre-filtered IF signal.

[ BTW, if the lowpass filter has (single-sided) bandwidth of BW, then the corresponding bandpass bandwidth is actually 2*BW, i.e. RBW is even wider. ]

Good points. These devices do not have a quadrature mixer, so your observations are valid indeed. The DC-path from the mixer output to the input of the low-pass filter (120 kHz RBW-filter) is dc-blocked, so there will be a problem with spectral components near 0Hz. Since the tracking generator and the receiver mixer are fed with two separate, independent oscillators, it may be possible to offset the receiver LO a bit higher or lower frequency*, sample the output of the 120 kHz RBW-filter with the SMT32F103 ADC, and then perform a complex spectral shift down to 0Hz in order to get a proper analytical quadrature signal, which should resolve this 0Hz problem. Please correct me I have have overlooked something.

*For example, If one wants to have RBW of 1 kHz, the receiver mixer LO needs to be offset at least by this same amount ie by 1 KHz. In reality, the offset needs to be a somewhat more because the spectral components near DC will be attenuated due to the DC-blocks in the signal path.
 

Offline KalvinTopic starter

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EDIT:
If the frequency response of the analog lowpass filter (on this web page) is correct, then digitizing is challenging, too. If I extrapolate the filter's transition band to -100dB below peak, then I get a required Nyquist frequency of about 4MHz, requiring a sampling rate of 8MSa/a. If only the (say) 0...300kHz band is eventually evaluated in the digital domain, then one could accept some foldback and allow a lower Nyquist frequency of (4000+300)/2=2150kHz. Required sampling rate were still 4.3MSa/s then. Depends of course on the desired image rejection (I assumed 100dB).

The noise floor of these boards is probably somewhere -70dB, so the filter's transition band attenuation may not have to go all the way down to -100dB. One option is to reduce the filter's bandwidth until the attenuation is sufficient for the sample rate and the desired dynamic range to be used.

STM32F103 seems to have a 12-bit ADC which is able to sample at 1 MHz. Since STM32F103 has only 20KB RAM, and STM32F103 may not be able to process the samples in real-time, the available RAM space will be a challenge and probably cause some pain during implementation and cause some compromises in the final design. But let's see.

Edit: Thank you for the link! It looks that the original RBW/low-pass filter is quite poorly designed, so the response can be improved by changing the component values. If nothing else will help, it is possible to design and build a new low-pass filter of higher order on a separate PCB, but at this point I would not consider this as an option yet.

Edit2: I wonder whether the DC-blocking capacitor at the output of the mixer could be removed, because the low-pass filter will be dc-blocked by its design topology anyway.
« Last Edit: May 12, 2021, 03:33:23 pm by Kalvin »
 

Offline gf

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The maximum dynamic range for these boards is probably somewhere -70dB, so the filter's transition band attenuation may not have to go all the way down to -100dB. One option is to reduce the filter's bandwidth until the attenuation is sufficient for the sample rate and the desired dynamic range to be used.

STM32F103 seems to have a 12-bit ADC which is able to sample at 1 MHz. Since STM32F103 has only 20KB RAM, and STM32F103 may not be able to process the samples in real-time, the available RAM space will be a challenge and probably cause some pain during implementation and cause some compromises in the final design. But let's see.

Edit. It looks that the original RBW/low-pass filter is quite poorly designed, so the response can be improved by changing the component values. If nothing else will help, it is possible to design and build a new low-pass filter of higher order on a separate PCB, but at this point I would not consider this as an option yet.

My 100dB image rejection desire was based on 70dB + (say) 30dB processing gain. 16-bit integer quantization (for calculations) were ~98dB, too.
If 1MSa/s is the limit, then I'd expect to end up with ~50..55dB, when allowing significant fold-back (again, granted that the depicted frequency response is correct).
According to AN4841, STM32F103 can do a 1024-point Q31 FFT in about 3ms. That were not too bad. 20k RAM is indeed pretty meager, though.
« Last Edit: May 12, 2021, 03:47:00 pm by gf »
 

Offline KalvinTopic starter

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The maximum dynamic range for these boards is probably somewhere -70dB, so the filter's transition band attenuation may not have to go all the way down to -100dB. One option is to reduce the filter's bandwidth until the attenuation is sufficient for the sample rate and the desired dynamic range to be used.

STM32F103 seems to have a 12-bit ADC which is able to sample at 1 MHz. Since STM32F103 has only 20KB RAM, and STM32F103 may not be able to process the samples in real-time, the available RAM space will be a challenge and probably cause some pain during implementation and cause some compromises in the final design. But let's see.

Edit. It looks that the original RBW/low-pass filter is quite poorly designed, so the response can be improved by changing the component values. If nothing else will help, it is possible to design and build a new low-pass filter of higher order on a separate PCB, but at this point I would not consider this as an option yet.

My 100dB image rejection desire was based on 70dB + (say) 30dB processing gain. 16-bit integer quantization (for calculations) were ~98dB, too.
If 1MSa/s is the limit, then I'd expect ~50..55dB, when allowing significant fold-back (again, granted that the depicted frequency response is correct).
According to AN4841, STM32F103 can do a 1024-point Q31 FFT in about 3ms. That were not too bad. 20k RAM is indeed pretty meager, though.

Let's think this backwards: What would be the maximum usable signal bandwidth at the output of a properly designed 4th/5th order low-pass filter when the sample rate is 1MHz, and the desired image rejection is 100dB (Zin=50ohms and Zout=1100ohms). After that we could gradually relax the filter requirements from 100dB down to 70dB, and see what bandwidth we will get using this current filter topology on the PCB.

Edit: Although the 20KB RAM is pretty small, the actual firmware is quite simple. If the algorithms do not use long sample buffers, then the RAM should not be a problem. What I have seen some alternative firmware implementations, they are quite straight forward and do not have any OS, so there is no need to allocate space for multiple stack frames, for example.

Edit2: One interesting observation from AN4841: STM32F103 can perform 1024-point Q31 FFT faster than Q15 FFT (214098 cycles/2.97ms vs 248936 cycles/3.46ms).
« Last Edit: May 12, 2021, 04:20:18 pm by Kalvin »
 

Offline KalvinTopic starter

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I was playing with this LC-filter design tool to get some idea what kind of performance is possible with the current filter topology available on the PCB: https://rf-tools.com/lc-filter/

The parameters I have used are:
- Low-pass
- Chebyshev or Elliptical
- Shunt first
- Order 5
- Cut-off 120 kHz
- Pass-band ripple 0.1 dB
- Input and output impedance 50

The Chebyshev gives 80 dB attenuation at 630 kHz, and Elliptical gives 80 dB attenuation at 492 kHz. Since the system is using 1 MHz sample rate, and we are mostly interested in the frequency components below 120kHz, we can tolerate some aliasing, and the MCU can perform additional filtering for the sampled data in order to attenuate the frequency components that are not in our interest and which are aliased.
 

Offline gf

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Let's think this backwards: What would be the maximum usable signal bandwidth at the output of a properly designed 4th/5th order low-pass filter when the sample rate is 1MHz, and the desired image rejection is 100dB (Zin=50ohms and Zout=1100ohms). After that we could gradually relax the filter requirements from 100dB down to 70dB, and see what bandwidth we will get using this current filter topology on the PCB.

Very rough estimate: 4th order is about 6*4=24dB/octave (at least asymtotically) => 100dB gives of cut-off of ~4 octaves below Nyqist then, or ~5 octaves below samling rate. When allowing significant fold-back across Nyquist, we gain almost one octave, leading to a low-pass cut-off of roughly 1M/2^5, i.e. ~30kHz (-> 60kHz RBW). In detail one would relly need to consider the actual filter design.

What is actually the oscillator frequency resolution (smallest frequency step)?
 

Offline gf

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I was playing with this LC-filter design tool to get some idea what kind of performance is possible with the current filter topology available on the PCB: https://rf-tools.com/lc-filter/

The parameters I have used are:
- Low-pass
- Chebyshev or Elliptical
- Shunt first
- Order 5
- Cut-off 120 kHz
- Pass-band ripple 0.1 dB
- Input and output impedance 50

The Chebyshev gives 80 dB attenuation at 630 kHz, and Elliptical gives 80 dB attenuation at 492 kHz. Since the system is using 1 MHz sample rate, and we are mostly interested in the frequency components below 120kHz, we can tolerate some aliasing, and the MCU can perform additional filtering for the sampled data in order to attenuate the frequency components that are not in our interest and which are aliased.

 :-+ 80dB @500kHz should be well sufficient.
 

Offline KalvinTopic starter

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Let's think this backwards: What would be the maximum usable signal bandwidth at the output of a properly designed 4th/5th order low-pass filter when the sample rate is 1MHz, and the desired image rejection is 100dB (Zin=50ohms and Zout=1100ohms). After that we could gradually relax the filter requirements from 100dB down to 70dB, and see what bandwidth we will get using this current filter topology on the PCB.

Very rough estimate: 4th order is about 6*4=24dB/octave (at least asymtotically) => 100dB gives of cut-off of ~4 octaves below Nyqist then, or ~5 octaves below samling rate. When allowing significant fold-back across Nyquist, we gain almost one octave, leading to a low-pass cut-off of roughly 1M/2^5, i.e. ~30kHz (-> 60kHz RBW). In detail one would relly need to consider the actual filter design.

What is actually the oscillator frequency resolution (smallest frequency step)?

The topology on the PCB seems to be 5th order, and if we use 120kHz RBW as our goal, and modify the filter to become Elliptical (by adding capacitors in parallel with the two inductors), we might be able to get theoretically 90dB ... 100dB dynamic range (including the processing gain).
« Last Edit: May 12, 2021, 05:06:27 pm by Kalvin »
 

Offline KalvinTopic starter

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What is actually the oscillator frequency resolution (smallest frequency step)?

The LTDZ board info says that the minimum frequency step is 1kHz. I am not sure if the steps become larger at the higher frequencies, as I have not looked at the ADF4351 datasheet in detail yet. https://www.analog.com/media/en/technical-documentation/data-sheets/ADF4351.pdf
 

Offline radiolistener

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I'm impressed with your desire, because working with ADC @ 1 MS/s on STM32F103 is a real headache  :)
 

Offline KalvinTopic starter

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I'm impressed with your desire, because working with ADC @ 1 MS/s on STM32F103 is a real headache  :)

Do not scare me! :) The plan is *not* to do any real-time processing at 1 Ms/s rate, but to get only the ADC samples into RAM buffer using DMA at the given sample rate, and then process the samples from the RAM buffer without actual real-time requirements. After processing the buffer, the system will start capturing the next buffer etc.. Since the available RAM is less than 20KB, the sample buffer and processing buffers may not be very long, but for simple signal analysis it should be sufficient. Even 1024 point FFT should be quite possible without any problems.
 

Offline KalvinTopic starter

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It would great to have a small bootloader installed into STM32F103, so that the firmware could be updated over the USB serial interface without any special development tools after initial bootloader programming. Any suggestions?
« Last Edit: May 12, 2021, 06:51:11 pm by Kalvin »
 

Offline radiolistener

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using bootloader is very inconvenient and problematic way to deal with STM32F103. There is JTAG/SWD connector on LTDZ board, so you can upload and download firmware with no needs for any kind of booloader. Also you can do incircuit debugging with it.

All what you need is just ST-LINKv2: https://www.aliexpress.com/item/32887597480.html

Original ST-LINKv2 has SWO signal which can be useful to receive debugging messages into terminal, but unfortunately such pin is missing on Chinese ST-LINKv2 clone. It doesn't limit you with in circuit debugging features, but printing debug messages over SWD interface is too slow. It will be better to have dedicated terminal through SWO pin.

If  you can find ST-LINKv2 with SWO pin it will be better, but also you can modding Chinese ST-LINKv2 to get SWO and RST for STM32 by soldering some wires:
https://habr.com/ru/post/402927/

PS: some years ago I bought this ST-LINKv2 for 1 USD, now it cost 4-5 USD  :o This is probably due to logistics issues...

By the way, here is firmware from my LDTZ instance. LTDZ bought from different sellers have different firmware, and a little different results and bugs. I don't know if source code is available, I just read it from my LTDZ with ST-LINKv2. Also I found that firmware build from sources for NWT D6 device works ok with LDTZ.
« Last Edit: May 12, 2021, 07:07:33 pm by radiolistener »
 

Offline gf

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PS: some years ago I bought this ST-LINKv2 for 1 USD, now it cost 4-5 USD :o This is probably due to logistics issues...
This is just the indicator for the true inflation rate ;)
 

Offline KalvinTopic starter

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Thanks for quick briefing for the tools, much appreciated! I do have bunch of those tools (probably got them also 1 USD each or something), but I have not been using them with STM32F103 yet.

The reason why I would like to have a bootloader is that after the actual firmware development is mostly completed, the enclosure will be closed, and the tools will be moved to some other project. In this situation it is much more convenient to use the bootloader to update the firmware than to open the enclosure once again, setup the development environment and close the enclosure. When I say a boot loader, I mean a custom bootloader that can receive a firmware [ASCII hex-file] over the serial port and Flash that into the memory. Thus, no need to install any special drivers other than the normal USB serial port driver, if needed.

My plan for the firmware development is as follows:

1. Create a simple STM32F103 firmware application which uses the serial port:
- command to to configure TX frequency of the ADF4351
- command to to configure RX frequency of the ADF4351
- command to start sampling the RX signal at 1Ms/s into RAM buffer
- command to dump the ADC sample buffer to PC over the serial port
- (command to update the firmware)
2. Do as much development on PC as possible, because it is much easier to do signal analysis and algorithm development on PC with proper tools.
3. After the algorithms are ready, implement the algorithms for firmware in C, and do the signal processing in STM32F103.
4. Create a simple GUI application for spectrum analysis (RX only).
5. Create a simple GUI application for filter and antenna measurement using the tracking generator.

I try to keep things as simple as possible, nothing fancy or bling-bling, only basic features. I will publish the project source code in Github after step 1, and keep it updated until step 5. After step 5 I may not be working actively on the project as it has served its purpose for me: The goal was to implement dynamically adjustable RBW for LTDZ platform, and as such make this inexpensive hardware more useful tool/instrument for amateur radio purposes. Since the source code will be freely available, someone interested in this project can fork my code, start adding the missing features and improve the GUI etc.

Edit: After step 1 and early step 2 it will be possible estimate how technically feasible this project will be. If it turns out that for some reason it is not possible to achieve the main goal of this little project (adjustable RBW with only minimum hardware changes), I will not proceed to steps 3 - 5. However, at this point everything looks pretty good, and no show stoppers are at sight.
« Last Edit: May 12, 2021, 08:11:35 pm by Kalvin »
 

Offline radiolistener

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here is some firmware source which I found. I don't remember if this source code works ok with LTDZ, but at least it compatible with LTDZ hardware and as I remember it even works. Just too lazy to flash it to test.

As I remember I found it on some site related to D6 device. This is not the same firmware as shipped with LTDZ, and it uses a little different device ID and use a little different protocol, but as I remember it works ok with LTDZ.
All things mixed together into single C file, but code is not too large so it is readable.

I didn't dig into source code deep, just tried to flash different versions and see how it works with LTDZ. As I remember, my NWTSHARP app implements both protocols, so it should works with original firmware and with this one. The difference with original is that one firmware requires to send sweep command with pause, otherwise it doesn't works properly. I don't remember exactly if it happens with original firmware or with this one.
« Last Edit: May 12, 2021, 08:38:35 pm by radiolistener »
 
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Offline gf

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Good points. These devices do not have a quadrature mixer, so your observations are valid indeed. The DC-path from the mixer output to the input of the low-pass filter (120 kHz RBW-filter) is dc-blocked, so there will be a problem with spectral components near 0Hz. Since the tracking generator and the receiver mixer are fed with two separate, independent oscillators, it may be possible to offset the receiver LO a bit higher or lower frequency*, sample the output of the 120 kHz RBW-filter with the SMT32F103 ADC, and then perform a complex spectral shift down to 0Hz in order to get a proper analytical quadrature signal, which should resolve this 0Hz problem. Please correct me I have have overlooked something.

For virtually any {desired input frequency, LO frequency} pair there exist an image input frequency, so that both (desired and image) input frequencies are down-converted by the mixer to the same IF frequency. Once the IF contains contributions from both input frequencies, they can't be separated any more unambiguously. So no, a digital down-conversion step after samling the IF cannot fix it either. Traditional superheterodyne radios solve the problem by ensuring that the image input frequencies do not even enter the mixer (-> band pass filter, tuned to the desired input frequency range, excluding image frequencies). If this is not feasible, then an image reject mixer or quadrature mixer is required, in order to either reject the contribution of the image frequency, or to retain the contributions of both frequencies in a separable way.

The tinySA avoids these issues by using a full-featured tranceiver chip, which includes LNA, VCO, quadrature mixer, IF filter, 2x ADC, some DSP processing, and which outputs the down-converted and decimated digital signal to the MCU.

Are you rather after SA functionality, or Network Analyzer functionality? While a SA has to deal with arbitrary input spectra, a NA only needs to receive/detect only a single frequency at a time (namely the current frequency transmitted by its tracking generator). The latter makes life easier.
« Last Edit: May 12, 2021, 09:04:45 pm by gf »
 


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