Author Topic: Idea for improving LTDZ Spectrum Analyzer & Tracking Generator 35MHz-4.4GHz  (Read 24171 times)

0 Members and 1 Guest are viewing this topic.

Offline gf

  • Super Contributor
  • ***
  • Posts: 1114
  • Country: de
After some thinking, this is not extraordinary difficult to implement, given that there are external relays and directional coupler/reflection bridge available, and the two ADF4351s can maintain sufficiently stable frequency.

It's a PLL, so once it is locked, the frequency ratio with regard to the xtal will be perfectly stabe. However, you need to give it enough time to settle after changing the frequency. The remaning "instabilities" are rather phase noise, eventually. The ADF4351 isn't that bad, though.

Quote
Since the tracking generator is sending a sinusoidal signal,

According to the datasheet (see attachment) It is not. So be prepared for mixing products having frequencies n * fIF (where n is an integer). I do not see a problem, though, to get rid of the IF harmonics by filtering. For instance, the frequency response of a one-period rectangular window (simple moving average filter) has zeros at all harmonics. If multiple periods are collect, then even more sophisticated window/filter can be used.

Quote
the RX can use whatever shifted IF and ADC sample clock that is suitable. For example the RX could use 12kHz IF offset, thus the ADC sample-clock needs to be at least 24kHz, preferably more like 4x, which makes signal detector quite simple. Since the ADC sample-rate can now be reduced from 1Ms/s down to 48Ks/s, ADC can be kept running continuously between different measurements, STM32F103 can process the samples in real-time, and the phase information between tracking generator and the LO can be preserved -> it is quite possible to implement a VNA with this hardware, external directional coupler/reflection bridge and external signal relays.

Likely you still want to run the ADC as fast as possible, in order that you can collect enough samples for suffient processing gain, w/o slowing down the measurements too much.

I also tried to find ADC characteristics for the STM32, like SINAD, SFDR, INL, DNL, etc. But I did not find any numbers :-//
Strange. For other serious ADCs I'm used to find these numbers and corresponding figures in the datasheets.

Btw, I also wonder, which of the STM32F103 models is it? And what's the clock speed?
is there a schematic of LTDZ available somewhere for download? My search was not successful.


I'm impressed with your desire, because working with ADC @ 1 MS/s on STM32F103 is a real headache  :)

Can you elaborate where exactly you did experience problems? One interrupt per sample is of course a no-go. But isn't it possible to setup free-running ADC with DMA (possibly with double-buffering if limited real-time processing were desired), steaming the converted data at the maximum sampling rate to memory w/o CPU intervention?
 

Offline gf

  • Super Contributor
  • ***
  • Posts: 1114
  • Country: de
After some thinking, this is not extraordinary difficult to implement, given that there are external relays and directional coupler/reflection bridge available, and the two ADF4351s can maintain sufficiently stable frequency.

It's a PLL, so once it is locked, the frequency ratio with regard to the xtal will be perfectly stabe. However, you need to give it enough time to settle after changing the frequency. The remaning "instabilities" are rather phase noise, eventually. The ADF4351 isn't that bad, though.

I just did take a closer look at one of the photos of the PCB. Are the ADF4350 clocked from a different xtal than the CPU/ADC? This would complicate things, since the frequency lock is not granted.
« Last Edit: May 16, 2021, 03:43:21 pm by gf »
 

Online radiolistener

  • Super Contributor
  • ***
  • Posts: 3222
  • Country: ua
Quote
Since the tracking generator is sending a sinusoidal signal,

According to the datasheet (see attachment) It is not. So be prepared for mixing products having frequencies n * fIF (where n is an integer).

yes, ADF4351 has nice square wave with rise time about 70 ps.
See picture with 40 MHz LTDZ output on 100 MHz oscilloscope.


Btw, I also wonder, which of the STM32F103 models is it? And what's the clock speed?
is there a schematic of LTDZ available somewhere for download? My search was not successful.

my LTDZ has STM32F103C8T6, it is clocked from 8 MHz oscillator. ADF4351 is clocked from separate 25 MHz oscillator.

I also didn't find schematic, but it looks that schematic is the same as D6 device, see attachment. At least LTDZ use the same components and firmware from D6 is compatible with LTDZ.

There is difference between this schematic and LTDZ on RF input, on LTDZ R16 = 51 Ω, but on schematic it R16 = 510 Ω. Looks just like mistake of manufacturer, because this resistor is marked as 510R on schematic, and they soldered SMD resistor with marking 510  :-DD

After some thinking, this is not extraordinary difficult to implement, given that there are external relays and directional coupler/reflection bridge available, and the two ADF4351s can maintain sufficiently stable frequency.

My LTDZ output frequency is not sufficiently stable. It has frequency drift, probably due to cheap 25 MHz oscillator. See picture with 1.5 GHz output. But I'm not sure, about the source of this drift, may be part of this drift is related with RTLSDRv3 oscillator. I'm using original RTLSDRv3 bought in official store.

I'm not sure if such drift is normal at GHz frequency, because I don't have experience with GHz band. I bought LTDZ as a startup generator for GHz band frequency. For short wave point of view such drift is awful.
« Last Edit: May 16, 2021, 08:15:51 pm by radiolistener »
 
The following users thanked this post: gf

Offline gf

  • Super Contributor
  • ***
  • Posts: 1114
  • Country: de
What units is the horizontal axis of the waterfall? Hz, kHZ, MHz? (I mean the zoomed one)
RTL SDR V3 is supposed to have a 1ppm TCXO (max. 1kHz drift @1GHz)

EDIT: If the scale is Hz, i.e. drift by only ~100Hz, then I'd say it is well within specs.

Quote
but on schematic it R16 = 510 Ω.
I guess the designation "510R" is possibly supposed to mean 51*100  \$\Omega\$
« Last Edit: May 16, 2021, 09:04:02 pm by gf »
 

Online radiolistener

  • Super Contributor
  • ***
  • Posts: 3222
  • Country: ua
What units is the horizontal axis of the waterfall? Hz, kHZ, MHz? (I mean the zoomed one)

Bottom waterfall units is Hz.
Top waterfall units is kHz.

When device is cold started (first 15 minutes), the drift is much worse. Even automatic frequency control cannot keep carrier within bandwidth, because carrier moving too fast. After 20 minutes board temperature is stabilized, but the drift still noticeable, when using SSB demodulation the tone shift is very significant.

For example here is 1.5 GHz drift after 10 minutes. May be it worth to replace 25 MHz oscillator with better one.
« Last Edit: May 16, 2021, 09:21:28 pm by radiolistener »
 

Offline gf

  • Super Contributor
  • ***
  • Posts: 1114
  • Country: de
If you need significantly better than 1ppm, then TCXO won't suffice any more and you rather need an OXCO.
Is the oscillator of the LTDZ actually a TCXO, or just a normal quartz oscillator w/o temperature compensation?
« Last Edit: May 16, 2021, 09:33:53 pm by gf »
 

Online radiolistener

  • Super Contributor
  • ***
  • Posts: 3222
  • Country: ua
I guess the designation "510R" is possibly supposed to mean 51*100  \$\Omega\$

I don't think so. Because according to the datasheet for IAM81008 mixer it's RF input VSWR about 1.4.

I suppose that IAM81008 input impedance is about 70 Ω. With 51 Ω resistor in parallel it give about 29 Ω impedance.

And this well corresponds with actual LTDZ input impedance measured as 30 Ω, see picture.

I also read some blog about LTDZ modification which recommends to remove 51 Ω and as result it leads to input impedance more close to 50 Ω. With such mod the input is more sensitive, which is good for spectrum analyzer mode. But also LTDZ output will be too strong and direct connection RF-IN to RF-OUT will leads to overload, so there is needs to use 10 dB attenuator.

If you need significantly better than 1ppm, then TCXO won't suffice any more and you rather need an OXCO.
Is the oscillator of the LTDZ actually a TCXO, or just a normal quartz oscillator w/o temperature compensation?

According to the marking this is VCC1 (Ultra Low Jitter, Fundamental or 3rd OT Crystal Design with 20ppm temperature stability). But who knows what exactly is installed on Chinese factory... :)
« Last Edit: May 16, 2021, 10:13:57 pm by radiolistener »
 

Offline gf

  • Super Contributor
  • ***
  • Posts: 1114
  • Country: de
20ppm is not very good, though. As already mentioned, RTL SDR V3 is supposed to have a 1ppm TCXO (i.e. 20x better), and an OCXO (crystal oven) can have a stability of even 10ppb. But I guess price of a good OCXO alone is likely higher than the price of the whole LTDZ board.
« Last Edit: May 16, 2021, 10:31:49 pm by gf »
 

Offline KalvinTopic starter

  • Super Contributor
  • ***
  • Posts: 2145
  • Country: fi
  • Embedded SW/HW.
Here are some pictures I found.

PCB:
1219852-0

Schematics:
1219854-1

They are from two different sites, but I believe they are both for the same LTDZ hardware.

The two ADF4351s are driven from the same 25 MHz oscillator, which is good news as they will be synced together and they will drift alike. It should not be too difficult to replace the existing oscillator with a better one.The MCU is driven by a 12 MHz its internal 8MHz oscillator. The MCU is either genuine STM32F103 or a clone. I do not have any detailed information about the ADC, but let's not hope too much from it - It is whatever it is.

Since the MCU is not using USB for the serial port (there is a separate USB-to-SERIAL-controller CH340G), it might even be possible to clock the STM32F103 from the same 25 MHz oscillator. That would make things a bit easier when implementing the PLL as all blocks are driven from the same clock. Just checked: The STM32F103 datasheet specifies that the maximum external clock frequency is 25MHz. Adding any extra wiring carelessly to the existing clock network may cause serious problems to the clock signal quality, however.

Edit: Corrected the MCU oscillator.
« Last Edit: May 17, 2021, 06:17:20 am by Kalvin »
 

Online radiolistener

  • Super Contributor
  • ***
  • Posts: 3222
  • Country: ua
20ppm is not very good, though.

yeah, but at least it is declared as ultra low jitter.

The MCU is driven by a 12 MHz oscillator.

no, MCU is clocked from it's own 8 MHz oscillator (see below the STM32 chip).

12 MHz oscillator is used for CH340 USB-USART converter chip.

Since the MCU is not using USB for the serial port (there is a separate USB-to-SERIAL-controller CH340G), it might even be possible to clock the STM32F103 from the same 25 MHz oscillator.

This is a bad idea, the clock ADF4351 will be more noisy due to interference from MCU. There is no sense to clock MCU from the same clock as ADF4351.
« Last Edit: May 16, 2021, 10:44:00 pm by radiolistener »
 

Offline gf

  • Super Contributor
  • ***
  • Posts: 1114
  • Country: de
There is no sense to clock MCU from the same clock as ADF4351.

For non-simultaneous phase measurements, it does make sense to have ADC clock, transmitter clock and receiver LO clock frequency locked to each other. NanoVNA uses a single clock source either, obviously for the same reason.

If this is not realizable, then a kind of software PLL were required to compensate the drift between ADC clock and ADF4351 clock.
« Last Edit: May 16, 2021, 11:09:56 pm by gf »
 

Offline KalvinTopic starter

  • Super Contributor
  • ***
  • Posts: 2145
  • Country: fi
  • Embedded SW/HW.
The MCU is driven by a 12 MHz oscillator.
no, MCU is clocked from it's own 8 MHz oscillator (see below the STM32 chip).

Thanks for spotting my error.  :-+ I fixed that in my post.
 

Offline KalvinTopic starter

  • Super Contributor
  • ***
  • Posts: 2145
  • Country: fi
  • Embedded SW/HW.
After some thinking, this is not extraordinary difficult to implement, given that there are external relays and directional coupler/reflection bridge available, and the two ADF4351s can maintain sufficiently stable frequency.

It's a PLL, so once it is locked, the frequency ratio with regard to the xtal will be perfectly stabe. However, you need to give it enough time to settle after changing the frequency. The remaning "instabilities" are rather phase noise, eventually. The ADF4351 isn't that bad, though.

Quote
Since the tracking generator is sending a sinusoidal signal,

According to the datasheet (see attachment) It is not. So be prepared for mixing products having frequencies n * fIF (where n is an integer). I do not see a problem, though, to get rid of the IF harmonics by filtering. For instance, the frequency response of a one-period rectangular window (simple moving average filter) has zeros at all harmonics. If multiple periods are collect, then even more sophisticated window/filter can be used.

Quote
the RX can use whatever shifted IF and ADC sample clock that is suitable. For example the RX could use 12kHz IF offset, thus the ADC sample-clock needs to be at least 24kHz, preferably more like 4x, which makes signal detector quite simple. Since the ADC sample-rate can now be reduced from 1Ms/s down to 48Ks/s, ADC can be kept running continuously between different measurements, STM32F103 can process the samples in real-time, and the phase information between tracking generator and the LO can be preserved -> it is quite possible to implement a VNA with this hardware, external directional coupler/reflection bridge and external signal relays.

Likely you still want to run the ADC as fast as possible, in order that you can collect enough samples for suffient processing gain, w/o slowing down the measurements too much.

Instead of implementing a digital PLL, I was thinking a bit simpler approach: If the system is using external relays, and the relays are controlled by MCU, the MCU could compute the phase difference as follows:

1. The relays are set so that the signal from the tracking generator is fed into RX, and the MCU is sampling the signal from the tracking generator. This signal from the tracking generator is the reference signal with the reference phase.
2. The relays are then switched to another position (while the ADC is still continuously sampling the RX signal), so that the ADC will now sample the signal we want to measure.

If the sample rate is low enough so that it can contain these two signals in one buffer, it is possible to compute the phase difference between these two signals. Granted, at very low signal levels the accuracy will suffer. It is also possible to use two separate buffers. Anyway, this was my thinking for using the slower sample rate. Frankly, I have not given too much thought to this yet, as this is kind of advanced feature.

I am waiting for my LTDZ to arrive. Meanwhile I am setting up the development environment for the project and studying the original source code. Yesterday I spent some hours banging my head to table while trying to get my st-link V2 dongles from eBay to co-operate with the bluepill boards I have. It was found out that the st-link v2 dongles work ok, but the markings on their enclosure are totally wrong. After finally opening one dongle, the PCB had the correct signal names printed on it, and voilá, it was possible to Flash the Blinky into the bluepill boards. It was also found that I have two different kind of bluepill boards: some boards with STM32F103 and some boards with something different. I could not get those other bluepill boards flashed with the tools that I had installed, but I guess would be possible. Yes, I was using Arduino IDE to test the dongles and the boards, but just wanted to see that the dongles work.
« Last Edit: May 17, 2021, 08:34:14 am by Kalvin »
 

Online radiolistener

  • Super Contributor
  • ***
  • Posts: 3222
  • Country: ua
if you want vector network analyzer, it's better to buy nanoVNA or nanoVNA2. LTDZ is a scalar analyzer and it don't worth to modify it, because it will cost you more than nanoVNA and as result you will get some kind of Frankenstein instead of device.


I bought LTDZ just as a signal generator from 35 MHz to 4.4 GHz.
RF input with IAM81008 mixer, second ADF4351 and logarithmic detector are just a nice addition.

Unfortunately output level is too low for my needs, so I'm using LNA module as an amplifier.
« Last Edit: May 17, 2021, 10:50:04 am by radiolistener »
 

Offline Bicurico

  • Super Contributor
  • ***
  • Posts: 1704
  • Country: pt
    • VMA's Satellite Blog
Quote
Unfortunately output level is too low for my needs, so I'm using LNA module as an amplifier.

The FW of the LTDZ and D6 devices can be modified in order to select at least 4 different RF output levels.

This is what Domenico did to the FW, which is available on my blog. It does not provide means for higher output level, but you can attenuate it, which could be nice if you are addinf an LNA module.

Regards,
Vitor
 
The following users thanked this post: radiolistener

Offline KalvinTopic starter

  • Super Contributor
  • ***
  • Posts: 2145
  • Country: fi
  • Embedded SW/HW.
if you want vector network analyzer, it's better to buy nanoVNA or nanoVNA2. LTDZ is a scalar analyzer and it don't worth to modify it, because it will cost you more than nanoVNA and as result you will get some kind of Frankenstein instead of device.

I have nanoVNA already. The point here is to modify this LTDZ a little (like fixing the low-pass filter's component values for better passband and stopband performance, and using the ADC as a power meter instead of the on-board AD8307). With a little help from DSP the performance of otherwise limited hardware design can be improved. This can be taken as a learning experience, too: This is my first STM32F103-based project. Although the board has its problems, the combination of the tracking generator, LO+mixer and STM32F103 provides useful platform to do some experimenting as well. It is interesting to see how far this limited hardware can be pushed.
« Last Edit: May 17, 2021, 12:04:57 pm by Kalvin »
 

Online radiolistener

  • Super Contributor
  • ***
  • Posts: 3222
  • Country: ua
and using the ADC as a power meter instead of the on-board AD8307

12 bit ADC has much worse dynamic range than AD8307. If you want to replace AD8307 with direct ADC, then you're needs to use at least good 16-bit ADC.

As I know STM32 ADC has ENOB about 8-9 bit = 56 dB.

For comparison, AD8307 has dynamic range 92 dB. This is 63 times better than STM32 ADC.
« Last Edit: May 17, 2021, 12:21:04 pm by radiolistener »
 

Offline KalvinTopic starter

  • Super Contributor
  • ***
  • Posts: 2145
  • Country: fi
  • Embedded SW/HW.
and using the ADC as a power meter instead of the on-board AD8307

12 bit ADC has much worse dynamic range than AD8307. If you want to replace AD8307 with direct ADC, then you're needs to use at least good 16-bit ADC.

As I know STM32 ADC has ENOB about 8-9 bit = 56 dB.

For comparison, AD8307 has dynamic range 92 dB. This is 63 times better than STM32 ADC.

So, you are suggesting that the dynamic range of the 12-bit ADC cannot be improved, and using a 12-bit ADC as a LOG-converter (ie. power meter) is doomed from the start because AD8307 has a theoretical dynamic range of 92dB as stated in its datasheet? And what is the real dynamic range achieved using AD8307 in the LTDZ and similar boards? It is not 92dB although it is stated in the AD8307 datasheet.

Edit: Think about SDR and how it works: With a receiver with a 12-bit ADC it is possible to listen to weak signals that are well below the ADC's 72dB dynamic range. Even those cheap SDR-sticks with only 8-bit ADCs can be used to receive signals that are well below the theoretical 48dB dynamic range. According to your statement above, this should not be possible. Although the STM32F103 has pretty bad ADC, the principles are still the same. At this point I do not have any clue what will be the practical noise floor limit with different digitally implemented RBWs on this hardware.
« Last Edit: May 17, 2021, 01:40:31 pm by Kalvin »
 

Online radiolistener

  • Super Contributor
  • ***
  • Posts: 3222
  • Country: ua
So, you are suggesting that the dynamic range of the 12-bit ADC cannot be improved, and using a 12-bit ADC as a LOG-converter (ie. power meter) is doomed from the start because AD8307 has a theoretical dynamic range of 92dB as stated in its datasheet?

yes, I'm sure that you will get much worse dynamic range if you exclude AD8307 from measurement.

And what is the real dynamic range achieved using AD8307 in the LTDZ and similar boards? It is not 92dB although it is stated in the AD8307 datasheet.

that's interesting question. I didn't tested LTDZ RF input dynamic range separately. I will try to perform some tests.

When using RF-OUT to RF-IN, the dynamic range is about 50 dB.


With a receiver with a 12-bit ADC it is possible to listen to weak signals that are well below the ADC's 72dB dynamic range. Even those cheap SDR-sticks with only 8-bit ADCs can be used to receive signals that are well below the theoretical 48dB dynamic range.

ADC dynamic range is specified for bandwidth = sample rate / 2. When ADC works at 28 MHz sample rate, it's bandwidth is 14 MHz and if you filter it to 500 Hz bandwidth you will get processing gain 14 MHz / 500 Hz = 28000 = 44.47 dB.

There is no any improvement due to DSP processing. It's just balance between bandwidth and noise level, nothing else. If apply analog filter 500 Hz to original signal, you will get the same result.
 

Online radiolistener

  • Super Contributor
  • ***
  • Posts: 3222
  • Country: ua
According to your statement above, this should not be possible. Although the STM32F103 has pretty bad ADC, the principles are still the same. At this point I do not have any clue what will be the practical noise floor limit with different digitally implemented RBWs on this hardware.

Processing gain depends on bandwidth reduction. If you use 1 MHz ADC, it has 500 kHz bandwidth and if you apply 120 kHz filter, you will get processing gain = 500/120 = 4.16 = 6 dB. ADC has about 56 dB, so in total you will get 56+6=62 dB. It cannot beat 92 dB of AD8307.

In order to get the same dynamic range as AD8307 on STM32 ADC with help of processing gain, you're needs processing gain = 92-56 = 36 dB = 3981. It means you're needs ADC with bandwidth 120 kHz * 3981 = 477.72 MHz. So, you're needs ADC running from 955.44 MHz clock.

STM32 ADC cannot run at 955 MHz and STM32F103 cannot process output from so high speed ADC. So, you will be unable to get the same dynamic range as AD8307 with using STM32 ADC directly.


By the way, don't forgot that dynamic range is limited not only with AD8307, but also with IAM81008 mixer and ADF4351 output phase noise. And it looks that the main bottleneck here is not AD8307, but IAM81008, ADF4351 and phase noise of 25 MHz oscillator.

By replacing AD8307 with direct ADC sampling you cannot improve dynamic range, because it is already limited on IAM81008 mixer output. And AD8307 already has much better dynamic range than you can achieve by using direct ADC sampling.
« Last Edit: May 17, 2021, 03:04:05 pm by radiolistener »
 

Offline gf

  • Super Contributor
  • ***
  • Posts: 1114
  • Country: de
Not only bandwidth reduction, but averaging of multiple measurements also results in processing gain - no need for 1GSa/s. It is just a matter of patience... :popcorn:
« Last Edit: May 17, 2021, 03:09:13 pm by gf »
 

Online radiolistener

  • Super Contributor
  • ***
  • Posts: 3222
  • Country: ua
Not only bandwidth reduction, but averaging of multiple measurements also results in processing gain.

averaging is a kind of low pass filter, so averaging is just a special case of bandwidth reduction.
 

Offline gf

  • Super Contributor
  • ***
  • Posts: 1114
  • Country: de
averaging is a kind of low pass filter, so averaging is just a special case of bandwidth reduction.

Sure, somehow it is. But it can be applied in a different domain, without reducing the (digital) RBW. Due to the DC-blocking analog IF filter, a too small RBW becomes conterproductive at some point, since it suffers from the analog filter's low frequecy attenuation then (so that even more processing gain were required to compensate that).
« Last Edit: May 17, 2021, 03:42:06 pm by gf »
 

Offline KalvinTopic starter

  • Super Contributor
  • ***
  • Posts: 2145
  • Country: fi
  • Embedded SW/HW.
Here are some pointers to books related this subject:

Freely available ebook "The Scientist & Engineer's Guide to Digital Signal Processing, 1999" by Analog Devices:
https://www.analog.com/en/education/education-library/scientist_engineers_guide.html

Freely available ebook "Software-Defined Radio for Engineers, 2018" by Analog Devices:
https://www.analog.com/en/education/education-library/software-defined-radio-for-engineers.html

Practical introductory book about digital signal processing without too complex mathematics (pun intended):
Lyons: Understanding Digital Signal Processing, 3rd Edition
 

Offline gf

  • Super Contributor
  • ***
  • Posts: 1114
  • Country: de
So, you are suggesting that the dynamic range of the 12-bit ADC cannot be improved, and using a 12-bit ADC as a LOG-converter (ie. power meter) is doomed from the start because AD8307 has a theoretical dynamic range of 92dB as stated in its datasheet? And what is the real dynamic range achieved using AD8307 in the LTDZ and similar boards? It is not 92dB although it is stated in the AD8307 datasheet.

Edit: Think about SDR and how it works: With a receiver with a 12-bit ADC it is possible to listen to weak signals that are well below the ADC's 72dB dynamic range. Even those cheap SDR-sticks with only 8-bit ADCs can be used to receive signals that are well below the theoretical 48dB dynamic range. According to your statement above, this should not be possible. Although the STM32F103 has pretty bad ADC, the principles are still the same. At this point I do not have any clue what will be the practical noise floor limit with different digitally implemented RBWs on this hardware.

Let's play with some numbers and visualize:

Low end of the AD8307's input range is specified with -75dBm. So let's set our aim at -75dBm, too. That's only about 40µVRMS. Let's try to capture that with the ADC. 40µVRMS is well below 1LSB. If it can be captured at all with the ADC, then only in the presence of sufficient dithering noise. Likely this is even granted per se, w/o explicitly adding additional noise.

I don't know the exact specs and operating conditions of the ADC, but let's make the following assumptions:
12 bits, full-scale input voltage = 2Vpp, ADC noise = 707µVRMS Gaussian noise (-30dBFS), wanted signal is sine wave with 40µVRMS.

Attached is a 10000 and 100000 point FFT of the simulated signal (with added noise and 12-bit quantization). Y-axis isnormallized to dBm input level (i.e. 0 is not full-scale)
With 10000 samples the noise floor can be lowered to a level such that the wanted signal peeks out a little bit. With 100000 samples the signal becomes clearly visible then.

So I guess it is not doomed from the beginning. But capturing that many samples takes some time. For input levels below say -50dBm, a LNA in front of the ADC were IMO helpful, in order that the ADC's dynamic range can be utilized more efficiently. Also unclear to me is the suitability of the existing noise for dithering such low signal levels (distribution unknown, while the simulation was done with perfect Gussian random numbers).

EDIT: I worry about potential unpredictable non-random noise/errors, though, like power supply ripple on the reference voltage (it seems not to be separately filtered?) and the bias for the input, unwanted coupling of stray signals, etc. Such things can still defeat feasibility.
« Last Edit: May 18, 2021, 06:05:07 am by gf »
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf