Is this noise for AD6645 ADC is acceptable or something is going wrong?

[radiolistener]

I'm debugging my circuit which consists of a high speed ADC and found some strange issue with ADC noise.

I'm using AD6645 ADC with AD8138 amplifier on the input. ADC is clocked from 96 MHz oscillator.

I'm capturing noise for open input (actually loaded with 50 Ω and 30 MHz LPF with open input) and found regular appearance of the same sample value several times in a row. For example, see picture below with a wave fragment of captured sample.

As you can see it has at least 4 samples in a row with the same value. This looks very strange for a white noise isn't it?

Why it may happens? Is it normal noise for a high speed ADC like AD6645? Or something is going wrong?

PS: When I do FFT, it shows pretty flat noise floor (see second picture). But there is also present some strange spur near 20 MHz and also some +20 dB low frequency spikes around DC with bandwidth of about 5-50 kHz, so I'm looking for the root of cause for these artifacts.

When low frequency spike appears, there is strange asymmetric pulses on the waveform (see third picture). I have no idea why it may happens. As I understand interference should affect both sides around mean signal value. Isn't it? Can it be related to the interferences on power supply wires?

[KE5FX]

The noise level is probably OK if you aren't normalizing the FFT to 1 Hz resolution.  If they used 32K FFTs for a 40 MHz spectrum in the data sheet (RBW = 2.4 kHz), which is typical, and got a noise floor near -112 dBFs, it'd be reasonable to see about -126 on your display at RBW = 92 Hz, where the noise floor will be 10*log10(2400/92) = 14 dB lower.

As for the interference, you can hunt that down by moving your clock a few MHz in one direction or the other.  Watch how far the spurs move.  That will tell you what Nyquist zone they're in, and thus their actual frequency.   Bear in mind that even though the data sheet says the input BW of the ADC is only 270 MHz, it will still be quite sensitive into the GHz range -- in other words, at frequencies where your 30 MHz LPF is probably re-entrant.

No clue re: the time-domain samples.  Ensure you have clean power, bypassed with small ceramic caps very close to the IC.  White noise is random, so I wouldn't worry too much about 4 samples in a row with the same value, but you do need to identify the source of the frequency-domain spurs.

[boB]

I would say that your FFT looks pretty darn good actually !

Yeah, move the clock like KE5FX mentioned to see if it moves too.

Try shorting the input too maybe ?   Without the amp.

boB

[radiolistener]

It was my mistake with absolute noise level. I got samples from hardware in two bytes format with a sign bit populated into unused bits. But when I do FFT, I load it as 16 bit range. So it shows level shifted for 6.02*2=-12 dB.

Here is fixed FFT for 1M and 32k sample for 14 bit range in attachment.

It looks that I have about 5-10 dB worse noise floor than expected from the datasheet (see example on page 12).

Hm... Is it possible that AD8138 add these 5-10 dB of noise?

[KE5FX]

Are you sure you didn't have it right the first time?  You were very close to Figure 22 on page 12, where they actually document the FFT size as being 1M points.

Otherwise, it could be a few different things, most likely related to data retrieval.  Feed it a single tone from a signal source of known amplitude, say -20 dBm, and see what dBfs amplitude is reported.  Typically about +10 dBm into 50 ohms will give you a fullscale reading, assuming unity gain. 

Obviously you can rule out the opamp by simply disconnecting it.

[radar_macgyver]

Hm... Is it possible that AD8138 add these 5-10 dB of noise?

What gain is the AD8138 configured for? With a high enough gain, one would expect to see the thermal noise power of the 50-ohm termination rise above the quantization noise floor. Could you post what you're using for the 96 MHz sampling clock? If it's a packaged oscillator, it is likely a third or fifth overtone type, so one would expect subharmonics. If you can, measure the sampling clock on a spectrum analyzer. 50 kHz is a common SMPS frequency, could be leakage through a power line.

Finally, what's the cause of the strong DC component? Is there a bias voltage being applied? Or is that just the offset voltage from the opamp? (sorry, I've only used such ADCs in transformer-coupled mode).

[Marsupilami]

Do you mind sharing the relevant part of your schematic? I'm not sure I get what you mean about the input termination.
The driver could easily cause the noise but it's suspicious to me how flat it is overall in the whole band so I would double (triple) check the FFT - power calculation too. Are you sure that your samples are interpreted correctly? You mentioned that you fixed a 16bit interpretations. What is the range you're getting now? Full scale should be +-8k in two's compliment.
The 4 consecutive similar samples look totally normal to me. The full swing in that section is 8 codes only and with white noise it's really easy to get 4 samples with the same value, especially close to the middle.
As macgyver wrote 50kHz is likely a switching power supply, the 20MHz I would guess is a clock leakage from your digital circuitry. (FPGA, DSP, MCU whatever)

[gf]

Hm... Is it possible that AD8138 add these 5-10 dB of noise?

What gain is the AD8138 configured for? With a high enough gain, one would expect to see the thermal noise power of the 50-ohm termination rise above the quantization noise floor.

Trying to get a rough idea what to expect:

The noise level of the ADC itself is already above the quantization noise floor. The datasheet specifies a typical SNR in the range 75dB_FS...72dB_FS. At 14 bits, this corresponds to an RMS noise level of 1.03...1.46 digital counts. At 2.2V full scale voltage, this corresponds to 138...196µV RMS, and spread uniformly of 50MHz (-> 100MSa/s) the density is 19.6...27.6nV/sqrt(Hz).

Table 8 of the AD8138 datasheet gives the expected noise levels at gain 1...10 (including the contribution from the R_G, R_F resistors), and they range from 11.6 to 70.8 nV/sqrt(Hz). If I assume a (single-sided) ENBW of 250MHz at 1x gain (just a guess, since the exact ENBW of the driver + ADC together is of course not specified), then this corresponds to 5 Nyquist zones at 100MSa/s, and folding them down to the first zone turns the 11.6 nV/sqrt(Hz) into 26 nV/sqrt(Hz). So the noise from the ADC and the noise from the ADC driver are suposed to have a similar order of magnitude. And at higher gain, the driver noise dominates.

@radiolistener, what is the standard deviation of the time domain samples? Since the noise floor in the FFT plots is very noisy itself, I'd rather focus on the total noise level which can be determined with much better precision. If no other signal component is present besides noise, then the standard deviation of the time domain samples is the RMS level of the noise.

[radiolistener]

What gain is the AD8138 configured for? With a high enough gain, one would expect to see the thermal noise power of the 50-ohm termination rise above the quantization noise floor.

It is configured for unity gain, both R_F and R_G = 510 Ω.
V_OCM is connected to ADC VREF pin.

Could you post what you're using for the 96 MHz sampling clock?  If it's a packaged oscillator, it is likely a third or fifth overtone type, so one would expect subharmonics. If you can, measure the sampling clock on a spectrum analyzer.

I'm using Chinese TCXO in a DIP package with no datasheet Yes, it looks that it has subharmonics oscillator inside and have some spurs, but it looks that it has better phase noise than other oscillators that I have at the moment, because when I use it I see not so much spike of noise floor around carrier from a clean carrier feeding at ADC input, other oscillators that I have are much worse than this one). Unfortunately I cannot measure it on a spectrum analyzer and there is no way to buy a new oscillator or other components, because there is a very difficult situation...

50 kHz is a common SMPS frequency, could be leakage through a power line.

Yes, probably it can be related to power lines for ADC. When I touch it, I see some change in these unwanted noise. But I can't figure out what's going on, because these changes are not reproducible and hard to predict. ADC has a capacitors and ferrite bead on power line near the chip, but probably this is not enough. Needs to experiment with better power line filtering.

I'm using Chinese linear lab power supply which powers two LT3042 based regulators to produce two separate 5V power, one for ADC and second for oscillator (through additional 3V LDO with capacitors and ferrite bead on oscillator board).

May be I have noise vulnerability in the power scheme, because there is 20 cm wires between power regulator and ADC board. When I touch these wires, I definitely see some changes of unwanted noise.

Finally, what's the cause of the strong DC component? Is there a bias voltage being applied? Or is that just the offset voltage from the opamp?

I think this is offset voltage from opamp. Zero voltage on opamp input leads to a some offset on the ADC output. When I test it, I found that I need to apply a little offset voltage on the input in order to use full scale.

I know that transformer provides better performance, and I have transformer for replacement. But it needs to desolder opamp for testing. At the moment I need ability to see low frequencies near DC for debugging, so that voltage offset is not an issue for me.

I'm not sure, may be that low frequency noise can be related with negative power line which is connected to the ground (for unipolar power mode). But it is connected to the ground on the power regulator side and there is about 20 cm of wires. I found a little voltage drop on a ground power wire, because ADC consumes about 270 mA. So actually opamp negative power line has a very small negative voltage which may depends on the current consumption of ADC. And another possible issue that I see is that 3 power lines can catch some noise from environment due to ground loops.

I tried to power opamp in bipolar mode and didn't get noticeable change, so I decided to return back to unipolar power mode which is more convenient.

Here is waterfall with a low frequency noise around DC component. Pay no attention to the RMS level, because it is shown for IF stream after DDC and LPF, I just added a little more attenuation for a FIR filter to avoid overflow for a full scale DC.