JLCPCB Impedance controlled trace is not the right impedance

[Xevel]

Hello,

I have a 4 layer PCB with a roughly 16mm feed to a Bluetooth chip antenna on TOP.
I tried to design it to be 50 ohms, but when I started testing the antenna performance it was wildly different from what I was expecting, so I started investigating and it seems to me that the first problem is that my transmission line isn't even close to 50 ohms.

I would be very appreciative if more experienced people could help me understand where I went wrong (if it's at the design stage, or the measurement stage, or something else altogether that I haven't considered).



The PCB : 4 layers, 1mm thick, designed for JLCPCB's impedance controlled stackup JLC7828.
JLC's [url=https://cart.jlcpcb.com/impedanceCalculation]calculator gives 11.55mil / 0.293mm line width for these specifications.
Saturn PCB gives a slightly different answer:
 - Microstrip, 18+18um copper, FR-4 with Er=4,6 (the dielectric constant for prereg 7628 according to JLC's page), conductor height = 0.2mm, F=2400 MHz  ==> about  0.35mm width to get 50ohms
 - Coplanar wave, FR-4 with Er=4,6 (the dielectric constant for prereg 7628 according to JLC's page), conductor height = 0.2mm, Gap = 0.18mm  ==> about  0.34mm width to get 50ohms

I  settled with 0.3mm for the first PCB prototype, since even according to Saturn PCB it gives about 53ohms, not wildly far off, and I would adjust for the next iteration.

That test PCB is aimed at testing the antenna and the effect of the parts around, some which have significant metal pieces (piezo buzzer, speaker), so I added two 0402 footprints to connect the feed + antenna to either where the Bluetooth chip is, or to a U.FL connector.
I realized a little late that the U.FL footprint might not be great with the thermal spokes so small, and on my test board I added a large solder blob on each side of the connector, but that's not the main point I think, since my big question is about the trace impedance.



So I will spare you most of the confusion of the initial tests and focus on the trace impedance.

After an OSL calibration with a cheap U.FL calibration kit (one on a RF demo kit like the ones people often get with a nanoVNA or similar) on my Siglent SVA1032X (CF=2441MHz, span=390MHz), I tried a sanity check : I cut and removed the trace at the place where it leaves the ground plane to go connect to the antenna (top right), populated the 0402 footprint to connect the U.FL and antenna feed with a 0R (thin film), and soldered a 49.9ohms 1% 0402 resistor  (green on the picture below). I was expecting something not too far from the center of the smith chart but to my surprise it wasn't anyway near (arc on a circle that crossed the horizontal line around 70 ohms, though I did not record that part exactly).




I tried the techniques from this link ( https://chemandy.com/technical-articles/measuring-track-characteristic-impedance/measuring-track-characteristic-impedance-article3.htm ) and this video ( ) to measure the impedance, and both gave roughly 40 ohms.

I cut the side of the PCB to verify the material thickness and measured 0.19 mm, a difference from the 0.2 that should make the impedance greater, not smaller, and only by a couple ohms.
Gnd plane is also well connected (I carved the PCB to make sure vias connected to it).

Any idea why my trace isn't the 50 ohms it should be ? or am I going in a completely wrong direction ?
Thanks in advance.


 

[T3sl4co1l]

So you get two different numbers, depending on how you measure it?

How about this, does the circle shrink to zero radius when the trace is terminated with another resistance (say 40 or 70)?  That's pretty characteristic, even if the rest of the system is being weird.

And this is at high enough frequencies where the trace is a wavelength or more, right?  (No scale factor was given, unless I want to compare in units of 0402 or u.FL footprints; and one CF+span was given, but unclear if that's the same for both tests?)

At a glance, I'd guess at 2.45GHz and a handful of 0402s in length, this trace doesn't matter very much.  But I don't know how tolerant your radio is, or how much tuning you expect to do on it.  Could just as well tune the antenna+trace as a whole? -- Which does require assuming your feedpoint is a correct reference (in terms of impedance and grounding), so there is still some value in checking that out, whatever the load or method.

Speaking of grounding, does it change with ferrite beads on the cable or anything?

Tim

[ThomasDK]

It's not the trace, it's the connector.

U.FL. connectors have a keepout zone:

[Xevel]

Hi, and thank you for the response.

So you get two different numbers, depending on how you measure it?

I haven't been very clear about that, my bad. When I did the sanity check and read about 70ohms (characteristic impedance), I hadn't played with the port delay at all and the length of the tested transmission line was close to 1/4 period, so maybe it was rotated 180° on the chart ? At that moment there was also the connector and 0R inline resistor in the picture, I might have messed thing up more than I realize...

How about this, does the circle shrink to zero radius when the trace is terminated with another resistance (say 40 or 70)?  That's pretty characteristic, even if the rest of the system is being weird.

interesting test, I will have to try again. The latest tests I did have been a little destructive though, I need to prepare another PCB...

And this is at high enough frequencies where the trace is a wavelength or more, right?  (No scale factor was given, unless I want to compare in units of 0402 or u.FL footprints; and one CF+span was given, but unclear if that's the same for both tests?)
At a glance, I'd guess at 2.45GHz and a handful of 0402s in length, this trace doesn't matter very much.  But I don't know how tolerant your radio is, or how much tuning you expect to do on it. 

Quite the contrary, the line is close to a quarter period (tests made around 2.4GHz so lambda is around 83mm with an assumed velocity factor of 0.66, and the trace I measured is about 16mm of uninterrupted copper, or about 20mm total in the tests with the connector and inline resistor ).

Could just as well tune the antenna+trace as a whole? -- Which does require assuming your feedpoint is a correct reference (in terms of impedance and grounding), so there is still some value in checking that out, whatever the load or method.

Thankfully I am not trying to get a best-in-class performance out of my BLE device, the way it's going to be used it really doesn't make sense that the BLE device and the host it talks to be separated by more than a meter. But I take that opportunity to try to understand a little bit better all that RF stuff.
Right now my problem is that I have multiple designs (physical PCBs on my desk) and I would like to compare them, but if even the most basic stuff (making a 50ohm transmission line) is wildly wrong - or I get wildly wrong results when I try to measure it, which would be even worse - I feel that I need to level up before going forward.

Speaking of grounding, does it change with ferrite beads on the cable or anything?

That part I found out about recently. 
My first tests I tried with a RG178 cable (SMA to U.FL, 150mm), and indeed I saw measurement changes when I handled the cable or touched the VNA connector. I added a ferrite bead and taped it in place on the cable close to the DUT, negating in large part that effect. However after a few more insertions of the U.FL connector, I realized the female U.FL connector of that cable was damaged (inconsistent results) and got rid of that cable.
Then I changed to a RG 1.13mm cable (SMA to U.FL, 100mm long) and this one did not seem affected. Touching the connector or cable did not show changes in the output anymore, so I did not put the ferrite back.

For the measurement  of the track impedance according to the first method (Chemandy), I used again a RG178 cable,  without connector on the DUT side. For that test I calibrated the VNA at the tip of that cable, with  open, solder blob for short, and 49.9 1% 0402 for load, then soldered directly on the PCB for the measurements(I measured between the 0402 pad at the bottom and the other end of the feed, top right in my first picture).

[Xevel]

It's not the trace, it's the connector.

U.FL. connectors have a keepout zone:

Urgh, now I feel foolish.. so any test that uses the connector is off, thanks !

With that out of the way, I still have a problem with the trace itself.
I applied the method from https://chemandy.com/technical-articles/measuring-track-characteristic-impedance/measuring-track-characteristic-impedance-article3.htm both on my trace (the largest uninterrupted part, so well away from the connector and its wonky footprint), and did the exact same test with a similar length of RG178 coax cable.
EDIT I used a frequency of 1500MHz for these tests as the length of the trace was about 16mm, and on the first page they make it clear that the frequency and trace length should lead to the trace being close to an odd number of times lambda/8 for accurate results. So I chose 1x lambda/8 as that's the only acceptable value for my setup (VNA goes to 3.2GHz but the RG178 cables are rated to 2.5Ghz). /EDIT

The measurement for the RG178 coax cable came out at 52.3ohms (which is close enough to the theoretical 50 +/-2 ohms of the cable datasheet, considering the errors I introduce at every step [calib with just a resistor or blob, soldering that piece of cable to the original coax cable with dirty pigtails for the braid, shortening of the transmission line when I put a solder blob to short it....]).



The PCB trace came out at 42.7 ohms.
The Saturn PCB computation adjusted with the measured material thickness says my trace should be 52.5 ohms with this geometry and the materials supposedly used by JLCPB in the fabrication of the PCB.

[T3sl4co1l]

Easy enough to cut out the offending ground area, of course.

Also, I'm not sure how much they recommend that (the keepout region), for purposes of simple mechanical clearance, and soldering, versus actual electrical performance -- not to say it wouldn't be fair to expect to see performance change in this case.

That is, metal under the connector reduces clearance to the, whatever underside features the part has.  On those, I think the center pin pretty much is exposed on the bottom itself, so we'd certainly want to clear any exposed metal, to avoid shorts in the first place; and that plus soldermask, may be a soldering issue as the connector may not sit flat (same reason against copper + soldermask under QFNs, etc.).

But yeah, also that such proximity means a locally low impedance.  It's not a big length, at least, so it might not make much difference on the measurement here -- also, if you can OSL cal after the connector, that obviously would help.

As for the spokes, I don't feel bad about it, but I suppose it doesn't hurt to improve.  Could even do some via-in-pad, if you don't mind the possible soldering quirks.  Which, this is just for testing protos, right?  That'd be pretty fair game then I think...  So then you could get the via fence all the way under and around the connector, which can help.

But also it sounds like it's not a big deal, you did have one case with proximity effects, but can blame the abused* connector, and a different one worked okay.  So that's good.

*The poor thing probably got, what, ten, eleven insertion cycles?  Such torture!

Anyways -- so you're more confident about the 42.7 ohm figure?  With the awful tolerances of proto builds, that sounds about as good as I would hope.  That's out by less than 20%, even!

Put another way -- uh, I suppose give or take mechanical tolerances, I don't know how exactly well you've measured the stackup -- the dielectric constant varies as well, so eh, it can be all over the place, even when the geometry looks right.

You can certainly pay for more, and maybe it would be worthwhile on a board that needs an optimized link -- and to boot, the antenna may vary on tuning, probably worth having a QA process for the whole output network (trace included) -- but for what you have it sounds like this will be fine, maybe shave the width a hair (literally, heh?) or something.

Tim

[MartinL]

I see a few sources of trouble here:

Firstly, I don't believe JLCPCB are actually doing impedance control on their service. All they're offering is a guarantee that you will get that particular stackup of materials - i.e. that your boards won't end up on a different 4-layer stackup because they got pooled with orders with different requirements.

Impedance controlled production involves you agreeing details with the manufacturer on which tracks are to be impedance controlled, what the target impedances are, how they will be tested and what your tolerances are. Test coupons need to be included in the layout. The manufacturer will tweak the geometry to what they think will work, and measure the coupons. If the results are not in spec, the boards will be remade. All of this takes time and costs money.

In recent years there seems to have been an increase in pool services offering an "impedance control" pool which is actually just a fixed stackup and a calculator.

The idea of a controlled impedance pool could potentially be done well if the supplier gave specific geometries for various transmission line types at common impedances, and guaranteed impedances of these to given tolerances through testing coupons on each panel. But that's not what JLCPCB are offering here.

Secondly, there is the issue of how to connect to your trace to test it. Usually the approach if you want to verify a trace impedance for a given PCB process, is to make a board that is just a straight line with an RF connector at each end, often SMA.

If you're trying to connect to a trace in the middle of an existing layout by soldering bits of RG178 to it, those joints are going to be all over the place in terms of impedance at 2.4GHz.

If the PCB process is consistent, then a reasonable approach is to make a test board with several traces each calculated for slightly different impedances, say from 30 to 70 ohm, all terminated properly in appropriate connectors. Then test what you actually get and choose the geometry that's closest, or a value interpolated between the two nearest.

But with cheap pool services, there's no guarantee that the results you get next time will be similar.

Ultimately you have to consider what you're trying to achieve and how much time and money you want to spend on it.

[KE5FX]

In addition what MartinL says, the notion of "impedance control" may mean that they adjust your trace widths as necessary, but nothing else.   If you didn't clear the L2 ground underneath the U.FL connector center pad, for instance, then you basically put a bypass capacitor across it.  It might be big enough to render the downstream trace size irrelevant.

This problem is especially acute when the fab uses only a single prepreg layer between L1 and L2 in the interest of making 50-ohm traces as narrow as possible.  Works great as long as you understand the downside, which is that you must clear the L2 ground beneath any feature bigger than, say, the pads for an 0402 component.

Finally, the best way to diagnose this sort of thing is with a TDR, either real or emulated.  If you know anyone who has a Tek 1180x or CSA sampling scope, or a microwave VNA with a time-domain option, now's a good time to make a lunch date.

[Xevel]

@MartinL @KE5FX Indeed, I see your point about "impedance control" at JLC. At no point they really cared about the actual impedance of my traces, they just provide a standardized stackup (who knows what the actual result is though...).
For production, of the final board, we will talk with the manufacturer about having real impedance control for the antenna line, which should make it there problem and release us from having to care about it.


So I guess I should make my peace with that PCB and remove the (obviously bad) connector and (impedance mismatched) feed line from the equation, right ?
Just cut the feed close to the antenna, solder a piece of coax there (like most antenna tuning method I've seen do), do an OSL calibration in place and be on my way to test my antenna ?

[MartinL]

So I guess I should make my peace with that PCB and remove the (obviously bad) connector and (impedance mismatched) feed line from the equation, right ?
Just cut the feed close to the antenna, solder a piece of coax there (like most antenna tuning method I've seen do), do an OSL calibration in place and be on my way to test my antenna ?

That's a reasonable approach, and if you attempt an OSL calibration in-place at the feed point then this will go some way towards eliminating problems from the coax-to-board joint. It's a lot more than many people do!

However, do be aware that for a small chip antenna or PCB trace antenna at 2.4GHz, the interaction with the rest of the board is significant. It's really best to think of the antenna as being formed by the combination of the driven element and the PCB ground plane, rather than just being the element itself. This is why all such antennas give very specific layout recommendations.

Adding a length of coax running back to your VNA changes the antenna geometry, and can give quite different results from what would happen without the coax present. You can easily find that you're mostly radiating from the coax.

A common mode choke around the coax, as close as possible to where it attaches to the board, would reduce this effect.

[ahbushnell]

It looks like there is ground plane on the same layer as your strip line then I assume ground plane underneath the strip line.  Was the signal plane ground included in the tool you used for impedance calculation.  That would tend to lower the impedance.  Also FR4 is not well known for controlled dielectric constant.  They make special materials for that. 

Good luck
Andy

[Xevel]

@ahbushnell
The main calculation I used is the one from Saturn PCB Toolkit, and the result is largely similar in "coplanar wave" with the gap used, or "miscrostrip" configuration.

Coplanar wave with 0.18mm gap : 51.5 ohms
Microstrip @ 2.4Ghz: 52.11 ohms
(all other specs kept identical otherwise)

When it comes to the dielectric constant the effect is also quite small in that calculator :
Er=4.9 => 50.69 ohms
Er=4.6 => 52.11 ohms
Er=4.3 => 53.66 ohms

[SQ9MT_PL]

use to simulate some program
e.g:
https://ee-training.dk/transmission-lines/transmission-line-loss-calculator.htm

[eb4fbz]

UFL Pin 1 pad is giant compared to the 50ohm line width. Also, avoid using thermal relief on RF grounds.

[neilhao]

My two cents,

JLC's PCB had higher Dk than other manufacturers, although they never mentioned that. According to my measurement, JLC's PCB do have higher Dk than others.

They are in the commercial war with other Chinese manufacturers right now, and they claimed to use 8 Glass Fiber Sheets for PCB but most other manufacturers' used 6 sheets.

More Glass Fiber Sheets will push up the Dk.

[Joel_Dunsmore]

There are a few tests you can do.  For the most part you do need more than 1/4 wavelength at the test frequency so more than about 1 inch at 3 GHz.  Calibrate to the end of an SMA cable, then you can add your cut-off piece of coax wtih your almost 50 ohm resistor soldered to the end and put data-into-memory.  This makes the center of the Smith chart referenced to your resistor value, whatever it is. Then unsolder the resistor, solder the coax to you line and the resistor to the far end to ground.  Measure on the Smith chart and it should start at low frequency in the center and form a circle (or half circle at least if it is exactly 1/4 wavelength). Take ZL=sqrt(Zref*Zcrossing) so if it crosses at 70 ohms, you line is sqrt(49*70)=59 ohms. If it crosses at 30 then your line is sqrt(49*30)=39 ohms.  This works as long as your resistor is small enough that the parasitic inductance doesn't skew results.

Of course the classic way is to use a TDR or the time-domain mode on a VNA  to measure the impedance by sweeping to a high frequency and reading off the resulting impedance. This is explained in chapter 4 of my book if you have an interest (section 4.7).  ( www.tinyurl.com/JoelsMicrowaveBook ) 

[thinkfat]

Your ground pour doesn't leave a lot of space next to the feed line. I try to keep at least 2 feedline trace widths of clearance. This Altium article talks about a "3W" rule for microstrip transmission lines: https://resources.altium.com/p/microstrip-ground-clearance-how-close-too-close

[Gerhard_dk4xp]

For me, the JLCpcb 4 layer process hits quite closely.
I think I calculated 11.44 mil for 50 Ohm on the top layer.
but did draw it as standard 12 mil trace; this was only needed
as a test structure.
On the left is the TDR-internal 50 Ohm line, on 3.6 div hor.
is the SMA connector; too large a pad for the multlilayer and
no cut out in GND. Then follows the 12 mil micro strip,
the unpopulated SMA and finally the NOTHING at its end.

The 12 mil seems a little too much, the calculated 11.44 mil
might fit.

Gerhard DK4XP

[erikka]

Gerhard,
Just to be absolutely sure about the design parameters.
You used 12mil microstripline on top layer with solder resist on top, inner layer 1 as ground?

Would there be any advantage of using a microstripline instead of a co-planar waveguide? I can imagine that the thickness of the prepreg between top layer and inner layer 1 is better controlled than the gap between the trace and top layer ground of the co-planar waveguide?

[Gerhard_dk4xp]

Gerhard,
Just to be absolutely sure about the design parameters.
You used 12mil microstripline on top layer with solder resist on top, inner layer 1 as ground?

Yes, exactly. Without the solder mask, the surface would be HAL, and the
thickness ill defined.  In CuNiAu finish, the nickel would probably have extra loss.

Would there be any advantage of using a microstripline instead of a co-planar waveguide? I can imagine that the thickness of the prepreg between top layer and inner layer 1 is better controlled than the gap between the trace and top layer ground of the co-planar waveguide?

CWG would radiate less. I just wanted to confirm that the short lines between the MMICs
and the SMAs work OK, the simplest use case. I don't think that the gap width would make a problem.
The SMAs definitely need rework for the multilayer, less wide center conductor
and maybe cutouts in inner level 1 metal.

In retrospect I wonder why I did not measure the line loss when I had
it on the table.

[erikka]

I will be doing a test PCB shortly with cutouts under the SMA center pins using CWG on top layer.
Will let you know the results.

[RoV]

Yes, exactly. Without the solder mask, the surface would be HAL, and the
thickness ill defined.  In CuNiAu finish, the nickel would probably have extra loss.

I'm not sure, but I am convincing myself that surface finish is a minor loss source for microstrip, because conduction current relevant to the quasi-TEM mode is mostly on the copper side looking at the ground plane. May be more critical for low-dk substrates like PTFE.

[ssturges]

I have done a lot of work on PCBs in my life and the Saturn models never match what the vendors do due to the finer effects.  We always used the stackup the vendor provided and trace widths they provided us.  I always thought that the vendors build a skew of boards and used that to tune a model of the process.   I have never see math models for the finer things like solder mask on RF traces, has anyone or can point to papers on the subject.  Funny we do all this engineer but in the end it almost seems like trial and error to get the final answer.   It makes simulation difficult on complex designs as you have do a lot of fudging to match the vendors results.

[Uky]

I think it was ISOLA that provided a paper many years ago that described the effects of manufacturing variations that, if left uncontrolled, would result in a Zo variation of a 50 Ohm "designed" strip in real life end up anywhere between 25 and 75 Ohm.

There are multilayer board manufacturing processes that affects this. One product that I came across some years ago had a number of wilkinson splitters arranged as striplines inside a board of many layers. Some boards passed the acceptance test, some did not. As it was discovered, the board fabricator had purchased all materials in the beginning of the process, boards and prepregs. As the time went by, the prepreg cured/stiffened and when pressing the finalized laminates together, the pressure could not be evenly distributed. As a result of that, boards close to the edges tested different than boards that was cut from the center of the finished manufacturing process.

If using RF-4 for eg. BlueTooth or any other application in the 2.45 GHz frequency range, I always check with the manufacturer from where he gets his laminates. What tolerances are available and also what granularity the board material in built up using. At least from ISOLA, there was a multitude of different board materials in the "FR-4" segment. Different thicknesses (of course), different resin/fiber content relationships, etc. When it comes to the relation between glass fiber and resin, this is of importance, since the glass has a different Er that the resin and if unfortunate, RF traces can end up right where the Er variation is large thus affecting the performance.

Having carefully specified the board/prepreg material, I also ask for tolerances and based on that calculate the widths for eg. 50 Ohms and then specifically sets this trace width as a qualifier. The manufacturer can then choose to make a test cupon on the frame outside the actual board and use this width for impedance control. Allowing a manufacturer to change trace widths leaves other parts, such a solder pads untouched. This is a disadvantage.

Sometimes, I see people making the mistake of doing all recommended things above and then forgetting the capacitive parasitic effect of (much larger) pads on footprints for eg. connectors placed in the design. The footprints may be OK when the thickness is say 1.6 mm but not when the thickness between a top layer and first inner plane is much less. In such cases, the inner ground plane may have to be opened and another one, using stiched vias placed deeper into the design.

When doing microwave design - be careful if using ferromagnetic materials for plating. Be careful if the copper is deposited onto the fiber glass materials in a galvanic process using carbon. (Easily checked by peeling of a bit of copper and checking for a black surface underneath). I do not think this is a commonly used manufacturing process today but should nevertheless be kept in mind.

For 2.5GHz, covering short lengths of RF-traces with solder mask is no problem, but on 5 GHz it is. There, the manufacturer should be contacted and checked what plating processes that is available. My personal favorite is silver without using nickel as intermediate layer.

 

 

[Gerhard_dk4xp]

We once built pipeline pigs, that are torpedo-shaped units that are pumped with the oil
through the gas pipelines and that drag 1024 ultrasonic heads behind them to measure
corrosion from the inside of the tube.
We used plugs etc from submarine companies etc but it is hard to keep gas/oil
vapours completely outside.
FR4 has the habit to absorb these vapours and the boards tend to swell when
it is too much. That can crack the vias open.
As a precaution, we had our our boards made from Kevlar. We got bitten by the
fact that the Kevlar prepregs have an unusually short shelf life.
Our nice 12 layer boards delaminated and took those Virtex FPGAs with them.
Beware of short delivery times. That may mean that your board house still has
stale prepregs from an earlier project.

Just to add insult to injury, our department head found our unused refused
boards on the booth of the board house on the Munich Electronica fair, as
proof of capabilities. Oh, he was fed up!