Layout for RF RX Circuit and Transmission Lines

[beeboopbeep]

Hi everyone,

I am designing an RF RX circuit (frequency of interest is between 10 MHz to 200 MHz) and had some questions regarding transmission lines. I used the impedance calculator tool (microstrip line) to find out which width will provide 50 Ohms and used it to complete the layout as shown in the attached picture. My questions are the following:

1) The impedance calculator provides impedance for a single route but does it also apply for routes where it splits like in the picture? (i.e., V_IN splits into 9 routes)
2) Will the SMA connectors for V_O_1 to V_O_9 greatly affect the impedance of the V_IN route since they're quite close to each other?

Note that J1 to J10 are female SMA connectors with through hole connections. Also, the total length of the circuit in the picture is approximately 9.5 cm. The V_IN routes that get split into 9 routes are terminated with a bypass capacitor (22 nF) and then to the rest of the circuit.

Thank you for your help!

EDIT: I forgot to mention that the bottom layer will be GND plane.

[Xnke]

The characteristic impedance will definitely change, that's not a microstripline, that's a signal bus.

In order to preserve the impedance characteristics, (which you don't really need in this case) you'd need to use a divider/combiner to maintain the match. Losses will be...high.

In your case, for a receive circuit like this matching the impedances is not a big deal unless you need to sqeeze the last few dB of signal out of the noise, and at 10-200Mhz bandwidth, maintaining that impedance match for weak signals is not the biggest worry.

[hagster]

Presuming the input impedence of each of those VO circuits is 50ohms, the input impedence at Rf_in will be about 5ohms. Thats a very bad impedence match to a 50ohm input. The length of the Tx lines is fairly short for most of your frequency range. The biggest issue is the divider network. Without more info on exactly what the circuit is, i dont think anyone can tell you the real world impact of this.

[beeboopbeep]

Without more info on exactly what the circuit is, i dont think anyone can tell you the real world impact of this.

The circuit is repeated 9 times, from top to bottom. For each circuit, the first component connected to the V_IN route ('50 Ohm' route) is a bypass capacitor (size of 0603) with a value of 22 nF. The rest of the circuit after the bypass capacitor is a mix of SMD resistors, capacitors, and RF MOSFETs where the 'main' RF MOSFET is configured as common-gate amplifier.

Also, I did some initial calculations regarding the circuit and it looks like for up to 200 MHz, the circuit is still considered electrically short (i.e., electrical length < lambda/20) as long as the SMA connector that will connect from the VNA to my circuit is short (< ~10 cm). Does this mean my impedance matching will not matter too much in this case as Xnke implied?

[Gribo]

An ideal resistive divider will give you ~9dB loss, a real resistive divider will be closer to 16dB loss. It is still better than the current 1:10 SWR.. Also, even for 200MHz, you might want to consider stitching vias near these RF traces.