Electronics > RF, Microwave, Ham Radio

PLL design with ADF4001 does not work

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Yrrah:
Nice measurements! I hope some day I can have the same results. I will look today with a friend. Must be something obvious or stupid. Will come back here.
My best, H

Yrrah:
It works!
The point is: you can not rely on the MUX output to observe the R and N counter input levels. The N counter output remains stable between less than -10 dBm until as high as +1 dBm and is quite tolerant about level. The R counter behaves almost the same but to establish reliable lock you need to provide at least +1 dBm. I operate the ADF4001 at +5V and then you need even more input signal (voltage). Refer to note 2 of datasheet, page 2. For the record: R Divider pulse width: 100 nsec, N Divider pulse width: 10 nsec.
To establish lock the CP cap is quite indifferent. I get lock from 100 nF to 100 uF. Of course loop dynamics is completely different....
Thanks to you for your comments. Highly appreciated.

G0HZU:
Sounds good now!

Your phase noise measuring stuff sounds interesting. I'm tempted to try this 102.4MHz VCXO to clock a fast DDS to see if the DDS can deliver low phase noise at output frequencies up to maybe 20MHz. I've got a couple of high performance spectrum analysers that can measure phase noise (in SSA mode) but the performance is a bit lacking in this respect. At work I have access to a couple of E5052A SSAs but I'd like to make something for home use too.

Yrrah:
For phase noise measurements at oscillators I have built a Phase Noise Testset by an article from DG4RBF, UKW-Berichte 4/2015. Not particularly easy to construct but it works good. Normal spectrum analyzers can not be used for serious phase spectrale analyses, as you know.
But this is another story....

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