Electronics > RF, Microwave, Ham Radio

PLL design with ADF4001 does not work

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Yrrah:
Hello,

I am trying to design a simple PLL controlled 100 MHz VCXO disciplined by a 10 MHz reference. The purpose is stabilize the 100 MHz oscillator while maintaining its good PN characteristics. I use a ADF4001 PLL chip in agreement with the datasheet, its registers are loaded with an Arduino. The ADF is fed by the Arduino 5V pin (for testing). I use the "Counter Reset Method", per datasheet. So far I have not even come to close the loop. I can load the registers with the proper counter data. Both input signals (100 MHz and 10 MHz via attenuators) are counted down to 25 kHz, the pfd frequency. They show up at the MUX output as needle pulses every 40 usec. I see some activity at the CP terminal with a scope via a 1kohm resistor. Then after a while the CP output keeps quiet and the N counter seems dead. The R counter works. I can not get out of this situation. I have made two testboards with the same results. Power up/down and reloading registers does not help. Is this a hw failure, a lock-in of the PLL chip or what? Before making a third board I'd like to know what to change....
Any help appreciated,
Harke, PA0HRK

KE5FX:
Assuming the charge pump polarity is correct, you might be overdriving it, or otherwise getting into a situation where it's trying to lock to a harmonic. 

The ADF4xxx parts are basically copies of the LMX2xxx parts from National Semiconductor, and virtually everything that applies to the LMX series applies equally to the ADF series.  NatSemi published a superb handbook of design info and troubleshooting hints for these PLL chips, known as "Dean's Book."  It's still available from TI, and is highly recommended.  The author is an app engineer who's seen every possible thing that can go wrong with these parts.  Whatever you're doing wrong, rest assured, he covers it.

HB9EVI:
how did you design the loop filter?

Yrrah:
Thanks for the link, John. Excellent reading!.
I managed to make the ADF4001 working again: I programmed all Timeout bits of the Function Latch to one. No clue. I also adjusted the input levels to about 3 dB above garbage. VCXO characteristics: Fnom=100 MHz, EFC: 1 kHz/V. EFC @ 100 MHz: 2.215 V. EFC input cap: 100 nF. Now its time to close the loop. With Vefc = 0V the VCXO frequency is little below 100 MHz. With Fref = 10 MHz the output of the CP is high (=+5V). Loop filter is calculated with ADIsimPLL. C1=31 nF + internal 100 nF. R1 =60.7 K and C2 = 633 nF. For a first test approximations are ok, I think. Loop BW = 10 Hz. Close the loop: CP stays high. Fvcxo is little above 100 MHz. No luck/lock. What else can I think of?
TIA, Harke

capt bullshot:
I've no idea if this helps, I'll post it anyway:
This is the initialization code I've used for a quite similar purpose ADF4001 circuit (control a 100MHz VCXO from a 10MHz reference).
I don't have the schematic of the loop filter available right at this moment, I might try to find it later today. It's a design made with the ADI PLL design software, I've chosen a higher order for better phase noise, afair about 20kHz BW.
In the first version I had the maximum charge pump current and a rather low PD operating frequency. In this version I'm using a higher PD frequency (yields better
phase noise results), but I had to reduce the charge pump current. With max. current, it was unstable.


--- Code: ---void adf_out(unsigned long v)
{
int i;
RESET_LE;
RESET_CLK;
for (i=0; i<24; i++) {
if (v & 0x00800000) SET_DATA; else RESET_DATA;
SET_CLK;
asm("nop; nop;");
RESET_CLK;
asm("nop; nop;");
v<<=1;
};
SET_LE;
asm("nop; nop;");
RESET_LE;
RESET_CLK;
RESET_DATA;
}

void init_adf(void)
{
unsigned long ref, n, func;
ref= (1 << 20) | // Lock detect precision
(0 << 18) | // Test mode bits
(1 << 16) | // Anti-Backlash width
(30 << 2) | // Reference counter //400
0x00; // Control bits
n = (0 << 21) | // CP gain
(300 << 8) | // N counter //4000
(0 << 2) | // reserved
0x01; // Control bits
func = (0 << 21) | // PD2
   (0 << 18) | // Current setting 2 /7
   (0 << 15) | // Current setting 1 /7
   (0 << 11) | // Timer counter control
   (0 << 9)  | // Fastlock mode / control
   (0 << 8)  | // CP Three-state
   (1 << 7)  | // Phase detector polarity
   (4 << 4)  | // Muxout control
   (0 << 3)  | // PD1
   (0 << 2)  | // Counter reset
   0x03; // Control bits
adf_out(func);
adf_out(ref);
adf_out(n);
}



--- End code ---

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