RF board design video

[KD0CAC John]

I saw this on one of my links I look most days , RTL web site  http://www.rtl-sdr.com/  , its the 2nd subject down page , I am using this link incase some haven't found it , it will be deeper in page as new subjects come up , but thought that it would give through link to other pages of interest RTL , Hackaday & source Great Scott Gadgets

[German_EE]

Most of what he says is good solid PCB design principles but I would add the following to his set of rules:

6) All high speed inputs and outputs (including RF) should be on an outside edge.

7) Decouple everything. A 100n capacitor to ground and a feedthrough capacitor on each power/control line as it enters the enclosure are the bare minimum.

If possible route your board so that adjacent inductors are at right angles to reduce coupling.

9) Cheap ceramic capacitors should only be used for decoupling and NEVER used in RF pathways.

10) If an IC has separate power and ground pins for analog and digital you need to follow the datasheet carefully and, if need be, split your groundplane.

[uncle_bob]

Most of what he says is good solid PCB design principles but I would add the following to his set of rules:

6) All high speed inputs and outputs (including RF) should be on an outside edge.

7) Decouple everything. A 100n capacitor to ground and a feedthrough capacitor on each power/control line as it enters the enclosure are the bare minimum.

If possible route your board so that adjacent inductors are at right angles to reduce coupling.

9) Cheap ceramic capacitors should only be used for decoupling and NEVER used in RF pathways.

10) If an IC has separate power and ground pins for analog and digital you need to follow the datasheet carefully and, if need be, split your groundplane.

Hi

I would suggest being *very* careful about splitting ground planes. Back when I was in school that was indeed the way it was done.  We all did it that way for many years. "Modern" high speed edges changed a lot of that thinking. Every course I have been to in the last 10 years or so makes this point. With modern logic edges (not clock speeds, just edges) splitting grounds may do more harm than good. I have also proved this on several boards before I learned what the issue really is.

Simple rule:

If you split a ground plane, you should be able to pick up the etched board and see light through the entire slot. *Nothing* solid (copper traces / other planes) should bridge the gap. That's not all you need to do, but it's a pretty good start.

Bob

[German_EE]

Interesting, so what would you do with something like an AD9951 DDS chip which has separate grounds and supplies for the analog and digital sections? I have a PCB using this chip that has a split groundplane running right underneath the chip and if I join them together I can see a measurable increase in unwanted spurs.

[Bud]

A few years ago i had emails exchange with an engineer from Analog Devices about a DDS, he said they usually use one solid ground plane for device characterizing, i.e. when building datasheets.

[Bud]

@German_EE

Look at DDS evaluation boards datasheets what they do, often ADI publishes the Gerbers for the boards.

[uncle_bob]

Interesting, so what would you do with something like an AD9951 DDS chip which has separate grounds and supplies for the analog and digital sections? I have a PCB using this chip that has a split groundplane running right underneath the chip and if I join them together I can see a measurable increase in unwanted spurs.

Hi

When I do an ADI part properly, the spurs go down. No, that's not some sort of "Bob knows best". The ADI split ground boards are a very commonly used "example" board in the typical class these days. They EMI guys go through the whole thing based on one and pop up their before and after data. I just follow along. Indeed there is more to it than just not using a split ground.

Bob