Author Topic: si5351 at 200 MHz  (Read 570 times)

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Offline bb1Topic starter

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si5351 at 200 MHz
« on: May 26, 2023, 02:44:47 pm »
si5351, being very inexpensive, is very popular as VFO.
For each output it uses two fractional dividers: One in fractional PLL, and the other to divide PLL frequency for the output.

Fractional dividers create spurs in the output. To decrease them, output divider is usually used in integer mode.
However, to provide enough frequency resolution, fractional divider should be used to set PLL frequency.

It is interesting to find how significant the spurs can be.
At low frequencies, such as around 7 MHz, spurs are low and difficult to observe.
To make them more visible, high si5351 output frequency around 200 MHz may be used.

If the PLL reference frequency is set to 25 MHZ, and si5351 output is set to 200 Mhz, then the output divider is set to 4,
and PLL divider is in integer mode with value of 32. In this case there should be no spurs.

which is screenshot of the Tek Spectrum Analyzer, confirms that.

The absolute frequency on the Spectrum Analyzer screen is not exactly 200 MHz because the si5351 reference frequency is about 100 ppm above 25 MHz.

However, small increase of the output frequency to 200.1 MHz leads to fractional PLL divider of 32.016, and radically changes the picture:

shows a lot of spurs, the largest ones being only about 25 db below the carrier.

It is interesting that 1GHz Tek scope infinite persistence does not show any significant jitter even at 200.1 MHz:

The following users thanked this post: rteodor

Online radiolistener

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Re: si5351 at 200 MHz
« Reply #1 on: May 26, 2023, 07:03:16 pm »
In order to reduce spurs, keep PLL frequency as high as possible. Many si5351 instances can run stable PLL above 900 MHz, but there is possible issues with PLL reset, if you overclock it it too much it may stuck in some state and require full power off to reset it (sofware reset and rewrite all register doesn't help). There is also some magic tricks to write some registers several times in order to keep it running stable in overclocked modes.

The problem with high frequency (above 100-140 MHz) is that it requires PLL reset so you can't sweep frequency smoothly. At low frequency you can change frequency without PLL reset and it allows smooth frequency sweep.
« Last Edit: May 26, 2023, 07:09:53 pm by radiolistener »

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