Tayloe Detector : 1:4 Mux Biasing

[jamfletch]

Hi Everyone,

I've been doing some reading on Tayloe Detectors, one thing I'm struggling to understand is the requirement for a DC offset at the input of the 1:4 mux. I've seen this in Tayloe's original paper here : http://www.norcalqrp.org/files/Tayloe_mixer_x3a.pdf along with a couple of example designs such as : https://github.com/thaaraak/Tayloe-Mixer-v2/blob/master/Tayloe%20Mixer%20v2.pdf

In Dan Tayloe's design, he biases up the RF input with a DC voltage prior to the multiplexer. At the outputs of the multiplexer, he uses AC coupling to the inputs of the Op-Amps, therefore I concluded the DC bias isn't required for the Op-Amps, but is for some reason used for the multiplexer. I've read the datasheet of the mux he's using here : https://www.diodes.com/assets/Datasheets/PI3B3253.pdf

I might be missing something obvious, I haven't managed to find an explanation online as to why the biasing is required. My only thoughts currently is that you may want to prevent the negative going part of the AC RF signal hitting the negative clamp voltage at the input?

Any help would be appreciated

[Kleinstein]

The CMOS mux chips may need the DC bias, as they can only handle signals inside the supply range (with only a little overrange). So the PI3B3253 and similar chips with single supply need the offset. A 74HC4052 could get away without it (e.g. with a +-5 V supply).  The amplifiers may get away without the AC coupling too, as there usually is not much DC offset in the result (a bit from coupling of the IF back to the input).

[jamfletch]

The CMOS mux chips may need the DC bias, as they can only handle signals inside the supply range (with only a little overrange). So the PI3B3253 and similar chips with single supply need the offset. A 74HC4052 could get away without it (e.g. with a +-5 V supply).  The amplifiers may get away without the AC coupling too, as there usually is not much DC offset in the result (a bit from coupling of the IF back to the input).

That makes sense, have I missed something in the datashet for the PI3B3253 that states that this is the required case for the inputs? It seems that there isn't any specification for required minimum input voltage to the switch inputs, only for the DC Logic

[mawyatt]

We found long ago that for RF signals where 3rd order non-linearity is of significant interest and minimizing such were major design goals (at the chip level), the simple NMOS switch was the best overall performer.

As mentioned keeping the input peak to peak signal within the switch voltage range, whatever switch type is used, is important for achieving acceptable overall linearity.   

You might find this of interest, please note the two IEEE papers and the impossible noise figures achieved, violating conventional mixer theory.

https://www.eevblog.com/forum/rf-microwave/polyphase-or-n-path-mixer/msg3381802/#msg3381802

Best,

[jwet]

Digital Bus switches (ie N channel only) are the standard for these circuits- they have low Ron when sourcing, low threshold voltage and are cheap.  CMOS type switches that use and N an P channel devices in parallel offer real advantages in discrete (non integrated) circuits.  We're not talking about 4052's, ADI/Maxim makes wideband, very low Ron switches- look at the Max4684 series- sub .5 ohm with .05 ohm flatness on 2.7v supplies- but there are many others.  These are exceptionally good switches for these applications and offer real benefits over Bus Switches.  I evaluated these ultra low Ron symmetrical switches for this mixer app and they showed a lot of advantages over bus switches.  I never published results because bus switches were so well accepted and were easier to integrate on commodity processes.

[iMo]

The switching speeds and capacitance plays a role there as well. I built several mixers with the 3253 (the softrock radios) and as I can remember they had struggled at say 28MHz already.

[tggzzz]

Another relevant figure of merit is the charge injection.

[mawyatt]

Digital Bus switches (ie N channel only) are the standard for these circuits- they have low Ron when sourcing, low threshold voltage and are cheap.  CMOS type switches that use and N an P channel devices in parallel offer real advantages in discrete (non integrated) circuits.  We're not talking about 4052's, ADI/Maxim makes wideband, very low Ron switches- look at the Max4684 series- sub .5 ohm with .05 ohm flatness on 2.7v supplies- but there are many others.  These are exceptionally good switches for these applications and offer real benefits over Bus Switches.  I evaluated these ultra low Ron symmetrical switches for this mixer app and they showed a lot of advantages over bus switches.  I never published results because bus switches were so well accepted and were easier to integrate on commodity processes.

Early on back in our chip development around 2005~6 we went thru quite a bit of analysis and simulation. For simulation we knew about the limitations of BSIM 3 and 4 CMOS models (issue with transconductance derivatives wrt to channel current direction), and utilized the highly compute intensive physics based PSP CMOS models which imposed all sorts of convergence problems as well as consuming massive computer resources.

What we discovered and much later confirmed by other researchers, is the Silicon Triple Well NMOS Switch produced the lowest odd-order non-linearity of any semiconductor technologies for a given switch area. This also benefited from a simple single phase switch drive voltage. The symmetrical CMOS switches worked OK but couldn't produce the same low levels of odd order distortion for a given switch area. Our interests were for high dynamic range wide-band frequency agile receivers at the chip level intended for future EW applications, so other application may have different requirements.

Also we found the 8 Phase Poly Phase Mixer (PPM) was the "Sweet Spot" wrt to mixer performance/complexity/clock-drive-speed, this arrangement "pushed" the first mixer harmonic response all the way to the 7th (maybe even 9th or 13th, memory is fading, see IEEE papers for details), so usually not an issue even with very wide band inputs.

Simple TSMC 65nm CMOS process, almost 2 decades ago resulted in above 2GHz performance for a 8 phase PPM, so one can imagine what is achieved today with sub 10nm technologies

Edit: For those not directly involved and/or familiar with CMOS technology wrt use in "analog" type environments, here's a link to Fujitsu 56GSPS dual 8 bit single chip ADCs developed in 65nm CMOS and introduced in 2009, soon after pushed to 64GSPS in 65nm CMOS!

As one can see quite impressive things can be done in just modest feature size CMOS

https://www.fujitsu.com/uk/Images/c45.pdf

https://indico.cern.ch/event/608587/contributions/2655890/attachments/1523991/2382089/Ping_Gui_TWEPP2017_ADC_Final_CERN.pdf

Best,

[jwet]

Maxim had a internal research program called "IQ"- innovation quest- where any engineer could propose a study and the CTO would provide funding.  It was designed to address designer's feeling like they were just grinding out designs and never got a chance to explore.  I was on the CTO staff and was kind of a guinea pig to motivate apps people as well.  I was playing with Tayloe Soft Rock type stuff in my Ham hobby and wanted to do a bit of testing with some of our sexy switches.  Frequencies were 1-50 MHz with some VHF playing.  The fast symmetrical switches showed well for dynamic range and some types of intermod.  The very best switches were not the ultra low on switches, like 1 ohm but more like 10 ohms- Max312 type.  Sort of a sweet spot of clean edges, capacitance, flatness, etc.  A modelling engineer in our TR&D group looked at my results and we discussed making a custom switch for the application but my little 60 hour research grant ran out and my boss wanted me to get back to work.  I haven't kept up with the literature but may go revisit.  I discussed once with Professor Lee from Stanford who was big in CMOS radios at the time.  Need to revisit I guess.  I can imagine getting down in the simulations would be daunting.  Its interesting to know that given your constraints, BUS switches came out best.  PMOS, with its much poorer mobility and specific Ron would gobble area that could be better used elsewhere.

Someone mentioned Charge Injection.  These types of drive contamination errors create less than perfect balanced mixers with LO feedthrough, etc.  Since mixers are cyclical,  unlike a sample and hold, a lot of the errors go away for the most part.  This is certainly true for real class H type mixer (hard switching).  One way of looking at Tayloe Mixers is as a  multi channel sample and hold so charge injection likely does play a larger role- its also cyclical and teasing out how all these distortion products settle out is not a trivial calculation.  Good observation.

[mawyatt]

That's great that Maxim recognized the value of allowing folks to innovate, we weren't as lucky and had to find "support" outside, usually DARPA, USG agencies and such.

Knew Robert Shear (was he the CTO can't remember) at Maxim way back, but long story. Same for Prof Tom Lee, we were on the original panel group with him that became/formed the IEEE MTT RFIC Symposium way back. Tom was adamant about CMOS for RF/MW/MMW, we preferred SiGe BiCMOS, guess who was right

Charge Injection was not usually a problem because it was stationary wrt the LO. It appears as LO leakage as small pulsed DC at the antenna, and cases where it could pose a problem Prof Molnar at Cornell came up with a way to minimize its' effect (don't recall if he published this).

Maxim was a great company for innovative semiconductor products, we did some work with early SiGe GST2, but another long story.

Fun stuff back then.

Best,

[jwet]

Pirooz Parvarandeh was our first formal CTO that put together IQ and a bunch of other progressive initiatives as we got bigger, siloed and saw the need to formalize that function.  Shear was a founder and was essentially the CTO for Maxim's first 20 or so years.  He ran a group called TR&D, Technology, Research and Development where process development, yield enhancement, failure analysis, modelling and CAD was run.  He also ran the FABs; Later, Fab operations and TR&D were split up and the CTO (Pirooz) ran it and a CTO organization.  Fab Operations was split off to group closer to test and back end there were some ragged edges like lithography and advanced yield.  Shear was an impressive guy and wore a lot of hats over the years.  I reported up to him in a corporate apps (business development) function that reported to TR&D before other re-orgs.  We were growing at 30%/yr for about 5 years and trying to figure out how it should all fit together took some iterations.

We had relationships with all the first class EE schools in the country and had very special relationships with certain Stanford, MIT, Berkeley and UCLA faculty and programs that usually involved Maxim sponsoring some work at those schools and the profs giving talks annually at Maxim.  Through formal means, alumnae or reputation, we had access to all of the important Analog academics and consultants on the planet.

Indeed fun times.