Trace Thickness and End-Launch for Impedance Calculations

[trophosphere]

Hello. I am currently working on optimizing a footprint for an end-launch SMA connector that I will be using for future RF projects. I am assuming that the end-launch's pin (PCB side) will affect the characteristic impedance of the trace that it lies on. For the purpose of calculating the characteristic impedance of that portion of the trace, would it logical to include the end-launch pin's diameter in the trace thickness portion of the calculation?

As an example using this end-launch connector.

For a GCPW trace with an approximate 50 ohm characteristic impedance:
Dielectric Constant: 3.66
Trace Width: 35 mil (Non-adjustable)
Dielectric Height: 56.28 mil
Trace Thickness: 1.7 mil (copper thickness plus plating) + 31 mil (end-launch pin diameter as specified in the datasheet) = 32.7 mil
Required Gap between trace and ground conductors on same side of the dielectric layer would thus need to be: 25 mil

[trophosphere]

Since I didn't get a response to my question (either I didn't explain myself clearly, no one knows, and/or it probably won't make a difference) I went ahead and did the next best thing by doing an actual experiment to determine if there is actually a difference. I am still in the process of learning RF so take the following with grain of salt plus please point areas that need to be fixed. The driving force behind all of this is because I am having a hard time believing I am getting so bad of a return loss with such a simple setup.

I drew up a small PCB which is composed of two grounded CPWGs whose ends are interfaced to an SMA end-launch connector on either side. The actual footprint for each SMA connector is the same. The difference lies in the gap width between the connector's signal pin pad and the adjacent ground. The top two SMA connector's signal pin pad has a gap width that is the same as the gap width surrounding the grounded CPWG. The bottom two SMA connector's signal pin pad has a gap width that is larger than the gap width surrounding the grounded CPWG. The enlarged gap width for the bottom two connectors was determined by adding the diameter of the connector's signal pin to the copper thickness. Note that the ground plane on the inner copper layer closest to the top copper layer has been removed for both versions (top and bottom) and extends as far as the end of each respective signal pin pad's gap to account for increased in pad width compared to trace.



To solder the SMA end-launch connectors I used a clamp to ensure that each SMA connector was pressed tightly against the board so that the gap between board edge and connector was minimized. I tried my best to ensure that the signal pin sat flush against the signal pad but wasn't too successful as any downward pressure on the board would compromise the horizontal alignment.



After the application of solder-paste and hot air the board looks alright. Some free solder balls are present which will be cleaned off prior to actual testing.





A look at the solder running along the gap between the signal pin of the connector and its respective footprint pad.





S11 and S21 for the top trace with the unmodified gap width



S11 and S21 for the bottom trace with the modified gap width



Conclusion: Widening the gap between the signal pin pad and the surrounding ground plane results in actual appreciable improvement in S11 (about 5dB better) as well as S21 (less ripple). Since the signal pin pad's width is already taken care of by removing the ground plane directly below the pad itself in the adjacent inner copper layer, one can assume the presence of the SMA connector's signal pin contributes additional capacitance (lower characteristic impedance) to the transition point between the end-launch connector and the grounded CPWG. Suffice it to say, it likely won't be as forward as just adding the diameter of the connector's signal pin to the copper thickness for calculating characteristic impedance but for a pinch it may be sufficient. Next step would be to increase the gap further and observe its effects (transitioning from a grounded CPWG to a quasi microstrip configuration at the site of where the connector's signal pin interfaces to its respective pad).

[LM21]

I have seen larger gaps between ground and the track. For instance 3W
https://resources.altium.com/p/microstrip-ground-clearance-how-close-too-close

[TheUnnamedNewbie]

This is definitely something you want to do. Ideally (especially if you go to >a few GHz) you want to start using an EM solver for this. In the end it comes down to effectively keeping the impedance of the line fixed. Since you have more capacitance to the ground plane (as you have a wide trace) you need to compensate that with less capacitance to the side grounds, and boosting the inductance a bit.

I usually include a 3D model of the connector in my simulations but have to admit I've never really looked at what happens if I remove it (ie, I can't say if it actually gives an appreciable capacitive loading compared to it not being there). I also usually work at frequencies north of 50 GHz, where these things will make a significant impact.
The connector vendor I usually work with provides detailed HFSS models to simulate with, but you may require an NDA with them to get them.

Good to see it in measurements!

[trophosphere]

I have seen larger gaps between ground and the track. For instance 3W
https://resources.altium.com/p/microstrip-ground-clearance-how-close-too-close

Thanks for the link. Definitely the gap would be much wider if I were going straight into microstrip territory. This is more to see if I can maintain a grounded CPWG from the board trace into the connector footprint rather than having to transition completely from one type of electrical transmission line type to another. I think around a little more than 1W of the trace for the gap width is the sweet spot for maintaining a good characteristic impedance at the end-launch's signal pin pad - for grounded CPWG type.

This is definitely something you want to do. Ideally (especially if you go to >a few GHz) you want to start using an EM solver for this...

I was thinking about using an EM solver such as OpenEMS but was unsure as to how accurate my models/available models for personal use will be as compared to just using a generic (but good) transmission line calculator like AWR Tx-Line from Cadence to get an acceptable starting point and just cranking out prototypes from there. I guess the value in an EM solver (besides many other things) is that one would hopefully obtain an answer that is much closer to the real world (to reduce number of needed prototype iterations) vs general ballpark but I am doing this on my own so there is really no deadline as compared to doing it as a business.

Wow, north of 50 GHz. I am guessing Satellite or 5G? I really doubt I will even touch that frequency range. I think I will stick to an order of magnitude below for now as I've seen the cost of those 1.85 mm connectors. I'll stick to my $3.93 SMA connector and if feeling fancy will occasional splurge on the $10.99 version.

[Marsupilami]

If you send me proper solid models of the connector and the pcb launch section I’ll run it for you in the simulator. It’s always an interesting challenge to match an existing measurement.