Which ICs are Appropriate for Generating Very High Speed Pulse Waveforms

[strahd_von_zarovich]

Hi everyone,
I need to design a high speed pulse waveform generator. Minimum pulse width must be lower than 300ps and rise-fall time must be lower than 100ps. Delay resolution must be lower than 100ps between channels.
What is the best way to do it. I worked on high speed DACs with JESD204B interface in the past. But I am not sure if it is the correct way to generate pulses.
Can you tell me what kind of ICs is the best choice for this purpose?

Thanks in advance.

[jonpaul]

No need of DIY, the leo Bodnar 40ps pulser generator is the best.
low cost, great specs.


http://www.leobodnar.com/shop/index.php?main_page=product_info&products_id=295
No connection just a satisfied user.
Jon

[joeqsmith]

What voltage levels?  Maybe add a timing diagram to show more overall detail?

[MathWizard]

I've never tried to make a fast pulse or make the fastest transition possible with my parts. I've made a few multi-vibrators w/ BJT's. I should try making 1 of them as fast as I can, on a copper clad board.

Pulse generator has low top-side aberrations

Impulse-response and rise-time testing often require a fast-rise-time source with a high degree of pulse purity. These parameters are difficult to achieve simultaneously, particularly at subnanosecond speeds. The circuit in Figure 1, derived from oscilloscope calibrators (Reference 1), meets the speed and purity criteria. It delivers an 850-psec output with less than 1% pulse-top aberrations. Comparator IC1 delivers a 1-MHz square wave to current-mode switch Q2-Q3. Note that IC1 obtains power between ground and –5 V to meet the transistors' biasing requirements. Q1 provides drive to Q2 and Q3. When IC1 biases Q2, Q3 turns off. Q3's collector rises rapidly to a potential determined by Q1's collector current, D1, and the output resistors combined with the 50 W termination resistor. When IC1 goes low, Q2 turns off, Q3 turns on, and the output settles to 0 V. D2 prevents Q3 from saturating.

I might try this Jim Williams circuit with an LM393 or IDK what I'd have close to the LT1394, I might have logic chips faster than the lm393 or lm311 I have.

https://www.radiolocman.com/shem/schematics.html?di=473679

https://www.analog.com/media/en/technical-documentation/data-sheets/1394f.pdf

[David Hess]

No need of DIY, the leo Bodnar 40ps pulser generator is the best.
low cost, great specs.

The Leo Bodnar pulse generator uses a fast comparator from Analog Devices.  The LVC logic family may be fast enough when run from a 5 volt supply.  And then that leaves the fastest ECL logic families.  The largest problem here is not actually the choice of logic family, but the physical packaging and layout to minimize parasitic elements.

RF transistors can also do it when used to make discrete ECL logic, but unfortunately RF PNP transistors which make this easier are not longer manufactured.

[KaneTW]

Hi everyone,
I need to design a high speed pulse waveform generator. Minimum pulse width must be lower than 300ps and rise-fall time must be lower than 100ps. Delay resolution must be lower than 100ps between channels.
What is the best way to do it. I worked on high speed DACs with JESD204B interface in the past. But I am not sure if it is the correct way to generate pulses.
Can you tell me what kind of ICs is the best choice for this purpose?

Thanks in advance.

Any FPGA high-speed transceiver with a suitable frontend.

[MathWizard]

So whats the rise fall time of stuff like 2.3GHz wifi stuff, or my 5.1GHz CPU ? And so what speeds are their oscillators ? I should get the calculator, but I have PCIe switches, and stuff off motherboards and GPU's. I guess they won't fit a breadboard. I never looked at any of that stuff in working operation, on a scope. Mine is 200MHz BW, I'd need one of those short ground prongs.

[KaneTW]

Yeah, try two orders of magnitude more BW on the scope to see modern high speed signals accurately.

[nctnico]

Hi everyone,
I need to design a high speed pulse waveform generator. Minimum pulse width must be lower than 300ps and rise-fall time must be lower than 100ps. Delay resolution must be lower than 100ps between channels.
What is the best way to do it. I worked on high speed DACs with JESD204B interface in the past. But I am not sure if it is the correct way to generate pulses.
Can you tell me what kind of ICs is the best choice for this purpose?

Thanks in advance.

Any FPGA high-speed transceiver with a suitable frontend.

I think this is a good starting point. Any FPGA a >10Gbit serialiser that allows to feed arbitrary data should do the trick. But it will be expensive.

[TERRA Operative]

I would look at the laser driver chips used for 100 Gigabit QSFP optic transcievers. They have gotta be at least a little bit fast.

But for a turnkey solution, I vote +1 for the Leo Bodnar solution, another happy customer here.

[nctnico]

But for a turnkey solution, I vote +1 for the Leo Bodnar solution, another happy customer here.

That does not meet the specs at all! Where is the 300ps pulse width??

[Marco]

Delay resolution must be lower than 100ps between channels.

Sounds like you want a multichannel digital delay generator, which is a harder problem than fast edges in most ways.

I think they are generally made by combining a programmable delay line with a coarser counter. Depending on how complex the signal have to be, you might be able to implement the coarse counter with just a micro and some discrete logic (the discrete logic doing the actual counting, to avoid the jitter from the micro). Though for complex pulse trains it's probably going to have to be done with a FPGA.

[David Hess]

I would look at the laser driver chips used for 100 Gigabit QSFP optic transcievers. They have gotta be at least a little bit fast.

I do not remember where, but I have seen some pulse generator output stages made from fast LED laser drivers.