White Noise Generator - Is there a chip combining LFSRs and analog output?

[abitofhelp]

Hello,

I would like to build a white noise generator using pseudo-random digital components.  I understand how to combine LFSRs with a low-pass filter to generate white noise.  However, I would like to know whether silicon chips exist that provide both LFSR binary generation and DAC analog output.  I've spent a few hours hunting online and have yet to find anything (i.e. Texas Instruments).  I am not an electrical engineer, so I may not be scanning the correct categories.  Could someone please tell me whether a chip exists with these features?  I know I could use a programmable chip, but I want to keep things simple.  This noise generator will be added to a noise-bridge in my manual antenna tuner.

[edit] After posting, I found that the DAC in STM32 products contains a white noise generator.  I am going to search online to determine if this is a common feature for DACs.

Thank you for your time and interest,

Mike

[ataradov]

Use any MCU with a DAC and a software noise generator. What is the actual problem here? Why do you need it to happen in the hardware?

[shabaz]

I don't entirely understand the problem being solved, either. I've never used a noise bridge and had to google it, and I may have gotten it wrong: Is it the case that you're trying to generate noise with a spectrum extending to, say, HF or VHF in an attempt to tune an antenna?

Ordinarily, a semiconductor junction can be used as a wideband noise source. It would be very unusual to do it with a LFSR for RF use.

Incidentally, the more usual 'offline' approach to measure impedance is to use a vector network analyzer VNA); it doesn't rely on any noise source. Nowadays, they can be quite low-cost (sub-$100), e.g. see 'NanoVNA'.

If your aim is to adjust your antenna tuner all connected up, then slightly cruder non-vector methods can be used; simply, measure the reflected signal during a very short burst of transmission (done with a bridge or directional coupler type of device). Ordinarily, this would all be automated (i.e., the antenna tuner components would either be electrically adjustable or switched in rapidly using relays under microcontroller control). This is a very effective and tried-and-tested method.

[ftg]

Why does the noise generator have to be digital, outside of it being a nifty project?

Manual antenna tuner seems to imply frequencies below 50MHz and around those parts one will get plenty of noise from a >16V Zener diode followed by suitable amounts of amplification.
The amplifying stages can be a handful of BJT's or something like 3x modern MMIC's in series.

[David Hess]

However, I would like to know whether silicon chips exist that provide both LFSR binary generation and DAC analog output.  I've spent a few hours hunting online and have yet to find anything (i.e. Texas Instruments).  I am not an electrical engineer, so I may not be scanning the correct categories.  Could someone please tell me whether a chip exists with these features?

Various sound chips for old personal computers and game consoles do that, however they have all been out of production for a long time.  These are intended for the audio frequency range so not suitable for RF applications.

I know I could use a programmable chip, but I want to keep things simple.  This noise generator will be added to a noise-bridge in my manual antenna tuner.

I suspect a zener or avalanche breakdown white noise source and amplifier like ftg suggests would be simpler, and I see many example schematics online.

[shabaz]

If you're curious about experimenting with LFSR, There's an ancient HP noise generator (might be HP 3722A, but I'm not sure; I've never seen it) that was described in a HP Journal article; it was based on a LFSR. In Art of Electronics (in the 2nd edition; maybe also 3rd) there's a design that looks very close to the HP one, and it's based on CMOS logic ICs from memory.

I decided to build, it, but kind-of made it on a single chip by simply using programmable logic (CPLD) instead of the individual logic ICs. The analog output relies on banks of resistors. Some op-amps are needed too admittedly, so it's not entirely single-chip.

Attached screenshot shows the type of output that is possible with it, I have no other measurements. And I was only shooting for 1 MHz, although really I had no purpose for any of it, it was more just to learn a little about programmable logic at the time.

It was a fun rainy-day project, but relies on lots of precise resistor values. If had to do it again I'd use a microcontroller or a DSP, and a DAC. For RF purposes all of this is most likely not of much use.

[dazz1]

Hi
I am looking at converting a pseudo random number generator bit stream to analog.  The HP 3722A used resistors to weight the bit outputs along the bit stream. The value of each resistor set the gain of each bit.   The weighted outputs were summed at a op-amp to produce an analog signal.  No DAC required.

The weighting could be applied in digital by ANDing each bit and a number representing the gain.  All the gains get summed, then averaged.  If the length of the bit stream is a multiple of 2, then the summed value can be divided with a register shift.    A bit stream 64 bits long would need to be shifted 8 bits to divide by 64 to get the average output (there is no requirement to divide by 64 because dividing random noise by a constant still equals random noise). 

The process of converting a bit stream into an analog noise signal could be done very efficiently in the digital realm.  All adds, shifts and, no multiplications.   This would be a good project for a FPGA.

[shabaz]

I think it's likely that the AoE 2nd Ed design is very closely based on the HP design. Looking at the HP Journal article briefly, it too uses digital filtering, just like the AoE design, using a sinc-shaped function, implemented with delay through the shift register, and resistors sized for the shape.

Anyway, I can confirm the AoE circuit does function. The 'scope screenshot in the earlier comment shows the AoE design, slightly modified (using a CPLD, and uprating the op-amps for better performance, since the AoE design only went up to 100 kHz from memory (I have given away my 2nd Ed copy, and can't find that design in the 3rd Ed, but may have missed it).

[dazz1]

Hi
I think after 60 years the HP algorithm is still fundamentally sound.  Advances in technology make it practical to put the signal path inside a device in the digital realm until a DAC converts to analog.  There have been some refinements that make the pseudo random number generator a bit more random, but really just polishing the boundary conditions. 

I think this would be an ideal application for a low end FPGA.  The problems are I already have too many projects in-flight and I don't have any experience with FPGAs.

[dazz1]

Hi
Looking a bit more closely at the problem, a DSP may be a better choice than a FPGA for something approaching a single chip solution, with supporting devices.  For a one-off project, using a dsp evaluation board may be a better solution than a design and build.

[shabaz]

I believe the problem is a noise bridge, so there's a possibility the noise is required for at least HF if not beyond. I don't know of a DSP Eval board for that. But I could be wrong. I had never heard of a noise bridge before. A semiconductor junction would be used for high frequency noise. Ordinarily these days other methods are used to tune antennas too. For instance, in a kind of "online" manner by measuring return loss and adjusting an L an/or C (often done automatically by a microcontroller). Or, offline, using a low-cost VNA would be another option. Both of these options require no noise source.

[Tation]

Hi
Looking a bit more closely at the problem, a DSP may be a better choice than a FPGA for something approaching a single chip solution, with supporting devices.  For a one-off project, using a dsp evaluation board may be a better solution than a design and build.

But there are mechanisms based on FPGA that produce true (not pseudo) random bit streams, in case you are interested on that. Simply search for FPGA based TRNG.

[dazz1]

Hi
Looking a bit more closely at the problem, a DSP may be a better choice than a FPGA for something approaching a single chip solution, with supporting devices.  For a one-off project, using a dsp evaluation board may be a better solution than a design and build.

But there are mechanisms based on FPGA that produce true (not pseudo) random bit streams, in case you are interested on that. Simply search for FPGA based TRNG.

Yes agreed, but the OP was pointing towards a minimum chip design.   For my application I don't want a TRNG.  For my applicatioin I need a HP3722A PRNG emulator to connect to my HP3721A Correlator.  I could use a FPGA for that but I think a DSP will probably do the job with fewer chips, and less cost.   If my application was more demanding, FPGA might be a better choice.  There is no single "right" answer here.  It is application specific.

[shabaz]

The AoE design is based on the HP design I believe, or it's very close. It uses logic ICs so it's very low cost. But all that is collapsible into a single CPLD. I know you mention you have no experience with FPGA, but actually zero experience is required; you can literally take the logic IC design and draw it out rather than use a HDL, because the design is so small for any typical CPLD. I believe it should be lower cost than a DSP board, plus would allow higher bandwidth most likely (I achieved > 1 MHz BW, without trying too hard, so say 10 MHz may be feasible, just speculating).

[dazz1]

I am only window shopping for design options at present.  I need to write down the specs and functional requirements before I start looking for a design solution.  CPLD and FPGA might be good for a pure noise generator, but I already know I will need data in/out interfaces, DAC, and controls.  Those are likely to require more code and design effort that the noise part.  Looking at the whole design problem, a DSP may be a better option for my application.

[radiolistener]

I would like to know whether silicon chips exist that provide both LFSR binary generation and DAC analog output.

I am looking at converting a pseudo random number generator bit stream to analog.

I just wonder - what is the reason to use DAC for noise generator?

From my point of view, using digital output of LFSR directly is better, than adding DAC in the chain. This approach not only maintains the properties of the noise but also offers slightly higher noise power and more wide bandwidth. In contrast, introducing a DAC in the chain seems to impact the noise flatness with much worse frequency bandwidth without providing any significant advantages. Isn't it?

[dazz1]

I just wonder - what is the reason to use DAC for noise generator?

From my point of view, using digital output of LFSR directly is better, than adding DAC in the chain. This approach not only maintains the properties of the noise but also offers slightly higher noise power. In contrast, introducing a DAC seems to impact the noise flatness without providing any significant advantages. Isn't it?

Read the HP Journal April 1971.
The analog output is generated by summing binary digital outputs.  Each binary is weighted (gain) with a resistor.  It is a non-linear DAC. 
In a DSP you could achieve the same by ANDing the binaries with numbers (gain), then summing to produce a single output value.  Apply this to the DAC.
This approach gives the option of staying digital, or going analogue. 

[Kleinstein]

For some application a pseudo random noise can be better than true noise, as it is more repeatable and predictable.

A white noise generator is a relatively low volume application - so well possible that there is no special chip. An FPGA or similar should a suitable solution for the digital part. For combining multiple bits, I see no need for different weights and precision. The sum of many non correlated random values converges to a gausian / normal distribution, even if the weights are off. So the "DAC" could be as little as a non critical resistor for each of the digital signals.

[shabaz]

Read the HP Journal April 1971.
The analog output is generated by summing binary digital outputs.  Each binary is weighted (gain) with a resistor.  It is a non-linear DAC...

Just to be a bit more precise(not that it matters if you're going a different route; this is more for anyone else interested), the HP design is more a kind of digitally generated filter (performing low-pass filtering through convolution rather than conventional RC or other op-amp based filters) attached to a binary pseudo-random stream, it too offers both digital out (i.e., that binary stream) and analog out. The net result is a digital-to-analog conversion; it's just that the way it occurs is slightly more sophisticated than might be expected when reading the comment about summing binary digital outputs.

[dazz1]

Read the HP Journal April 1971.
The analog output is generated by summing binary digital outputs.  Each binary is weighted (gain) with a resistor.  It is a non-linear DAC...

Just to be a bit more precise(not that it matters if you're going a different route; this is more for anyone else interested), the HP design is more a kind of digitally generated filter (performing low-pass filtering through convolution rather than conventional RC or other op-amp based filters) attached to a binary pseudo-random stream, it too offers both digital out (i.e., that binary stream) and analog out. The net result is a digital-to-analog conversion; it's just that the way it occurs is slightly more sophisticated than might be expected when reading the comment about summing binary digital outputs.

And the benefit of setting the gain of each bit with a stored digital number rather than fixed value resistors is significant.   The resistor solution requires a bag full of weird value precision resistors plus multiple op-amps circuitry.
In contrast doing the same in software eliminates the resistors and opamps.  Calibration and output accuracy would be much improved.  DAC errors would be compensated out in software.

[Kleinstein]

I don't think one would need special resistors. The logic choice for independent digital signals would be roughtly the same value for all, like from a bag of 5% parts.  An FPGA should be good for multiple LFSRs and thus multiple signals to mix. Different resistor values would be a thing when taking bits from just 1 shift register and do the digital filter math with resistors instead of digital.

The digital filtering may still be a bit more effective in filtering out the higher frequencies, where the time quantization would be an issue. So it could simplify the analog filtering part and maybe precompensate for the some of the analog filter roll off.

[iMo]

FYI - this is the noise generator I was using as the uni student in our lab - digital one but built on transistors.. Great machine, indeed.
Below the link to a 245 pages long manual with interesting insights, principles, math, measurements and schematics
https://pearl-hifi.com/06_Lit_Archive/15_Mfrs_Publications/20_HP_Agilent/HP_3722_Noise_Gen.pdf

[dazz1]

Hi
The HP 3722A Noise Generator was built to link with the HP 3721A Correlator I have and the HP 3720A Spectrum Display I don't have.  A 3 piece set.
Ideally I'd like to buy a 3722A but unlikely any ever imported to my country.  The cost of importing one, even if I could find a reasonably priced good unit, would be eye watering.

[Tation]

I don't think one would need special resistors. The logic choice for independent digital signals would be roughtly the same value for all, like from a bag of 5% parts.  An FPGA should be good for multiple LFSRs and thus multiple signals to mix. Different resistor values would be a thing when taking bits from just 1 shift register and do the digital filter math with resistors instead of digital.

The digital filtering may still be a bit more effective in filtering out the higher frequencies, where the time quantization would be an issue. So it could simplify the analog filtering part and maybe precompensate for the some of the analog filter roll off.

The signals are not independent, all are the same signal delayed 1,2,3 and so on cycles. There is/are 1 or more LFSR generating a single random bit sequence, followed by a n bit shift register, the outputs of this shift register are analogically weighted and then added. It's a FIR filter applied to the random bit stream. Thus the resistors are proportional to the coefficients of such FIR filter.

Did that many years ago (almost 40!), approximating a raised-cosine filter when there were no fast enough DSP available. Used an array of 64 multiturn potentiometers. Worked, but today I"ll try to use another approach...

[TimFox]

The National MM5437 noise generator IC is long gone.
Its original use cases included electronic musical instruments and acoustics testing.
I did see one from a surplus vendor advertised for $35, but it is now out of stock.
https://w140.com/tekwiki/images/2/29/MM5437.pdf

[radiolistener]

Read the HP Journal April 1971.
The analog output is generated by summing binary digital outputs.  Each binary is weighted (gain) with a resistor.  It is a non-linear DAC. 
In a DSP you could achieve the same by ANDing the binaries with numbers (gain), then summing to produce a single output value.  Apply this to the DAC.
This approach gives the option of staying digital, or going analogue.

This clarifies the functionality of the LFSR but doesn’t address the rationale for placing a DAC between the LFSR and the output.

Do I understand correctly that the DAC is intended to act as a filter to shape the flat noise response of the LFSR into a specific curve?

What specific frequency response are you aiming to achieve using the DAC as a filter?


For example, here is the spectrum of digital noise (direct output from LFSR):



And here is the spectrum of analog noise (using DAC between LFSR and output):



I don't see significant difference, except a little ~3 dB noise power offset. So, I'm trying to understand the reason to use DAC for noise generator...

[dazz1]

Do I understand correctly that the DAC is intended to act as a filter to shape the flat noise response of the LFSR into a specific curve?

What specific frequency response are you aiming to achieve using the DAC as a filter?

All is explained in the HP Journal attached to an earlier post.  My minimum requirements are to emulate an HP 3722A Pseudo Random Noise Generator.  I am a long way from starting any serious design work.
The HP 3722A implements a non-linear DAC with resistors and op-amps.  As mentioned above, this also implements a Finite Impulse Response (FIR) filter.

[dazz1]

I don't see significant difference, except a little noise power offset. So, I'm trying to understand the reason to use DAC for noise generator...

You need to look at the probability distribution function, and read the HP Journal. 

[radiolistener]

You need to look at the probability distribution function, and read the HP Journal.

Does it really matter when the LFSR is clocked at a sufficiently high sample rate from a non-synchronized clock source? The output will naturally undergo low-pass filtering through the output driver, which should result in a good natural distribution, which will be even better due to asynchronous clock. Isn't it?

I'm interested in this, because in such cases I usually just use digital noise with the maximum sample rate, but maybe I'm wrong and this can lead to some disadvantages?

[dazz1]

Does it really matter when the LFSR is clocked at a sufficiently high sample rate from a non-synchronized clock source? The output will naturally undergo low-pass filtering through the output driver, which should result in a good natural distribution, which will be even better due to asynchronous clock. Isn't it?

I'm interested in this, because in such cases I usually just use digital noise with the maximum sample rate, but maybe I'm wrong and this can lead to some disadvantages?

It depends on the application.    The HP 3720A Spectrum Display has a frequency range of 0.005Hz to 250kHz.  Some more reading attached.

[Kleinstein]

If an asynchronous clock is good or bad depends.
A 250 kHz max. bandwidth suggests some 5 MHz as maximum clock. So not expecially fast. HP3722 even uses a reduced clock to get a reduced BW part, so that more of the dynamic range is used. This could be in part also to have the same clock for the delay to use in the correlator. With the full clock one would need more memory / shift registers for the delay function there. A modern correlator would be more using 2 ADC channels and math to get the correlation function for many delays at the same time.

The coeffcients / resistors of the semi digital delay line filter should not be that critical. Any error there can effect the filter roll off a little, but not that much. The sinx/x scaling gives the brickwall type filter, but even with small errors in the filter one still gets a good low pass. One still has the analog LP filter anyway, that is not that ideal in the transition region.  I would consider some 16 odd resistor values (2x used each) not that bad. Even if 10% off, the respose curve of the filter would not be that much different from the ideal case and much would be towards the higher frequencies that are of little interest. There is anyway a none ideal response from the limted length of the sequence (32 bits in the HP7322).

[dazz1]

Using code rather than resistors has a number of benefits.  One of which is to significantly reduce the parts count.  Also easy to add self calibration feature.  Also software control of the FIR response including using an IIR filter.  All software selected.

By modern standards 250kHz is positively pedestrian.  It should be relatively easy to use a low spec, low cost DSP to emulate the HP 3722a. Such an instrument is likely to be of interest the modular audio synth crowd.

[dazz1]

If an asynchronous clock is good or bad depends.
A 250 kHz max. bandwidth suggests some 5 MHz as maximum clock. So not expecially fast. HP3722 even uses a reduced clock to get a reduced BW part, so that more of the dynamic range is used. This could be in part also to have the same clock for the delay to use in the correlator. With the full clock one would need more memory / shift registers for the delay function there. A modern correlator would be more using 2 ADC channels and math to get the correlation function for many delays at the same time.

The sample period is in the range 1s to 1us with a processing time of 136us.
An external clock can be applied to extend the clock period.
250kHz can be used with real data for the Correlator at a higher data frequency so long as the statistics of each sample remain the same.  Nyquist does not apply.
The Correlator can only process 100 samples but it can step along the noise signal in the time domain to extend the number of samples.    This is how the system can get down to the 0.005Hz freq.  Nyquist does apply.
The pre-GPIB 50 pin interface allows for control and export of data streams. 

The HP3722A, HP 3721A and HP3720A were designed and built run together so their specs compliment each other.