I've noticed the changes in red, only that I'm not convinced they are necessary. Here's what my doubts are about:
- the additional 0.1uF at the input of the 71L05 is not needed, particularly when the power source comes from a battery. Adding a 0.1uF is a thumb rule, but the existing C1/1uF MLCC already has very low ESR, another 0.1uF won't help.
- 10uF instead of 1uF (the cange of C1/C3) might get the LCO to behave even worst, particularly the C3. I've looked yesterday in the datasheet of a few 78L05 manufacturers, they recommend smaller C1/C3 values, and they don't use a second 0.1uF neither at input, nor at the output.
The thumb rule of adding 0.1uF decoupling does not apply to voltage regulators, in general. In fact, for some other regulator models (not 78L05), adding a 0.1uF MLCC might turn them into oscillators, because MLCC capacitors have very low ESR.
- same for the C2/0.1uF at the output (existing in the unmodified version), not needed. C2 should have been placed near the ATmega Vcc pin on the PCB, and unfortunately it was placed near the 78L05 instead. I guess things got mixed during the PCB design. This comment is not about the changes in red, but about the misplacing of the C2 on the PCB design.
- because of the above PCB design pitfall, the C* you added should be beneficial, I'll add those too, just that I didn't mentioned them as critical in my previous post
- the R* of 2k7 seem too big. I guess the reasoning of adding them was to limit the maximum current into the LCD pins, but the R* combined with the input capacitance of the LCD pin will make a low pass filter (will damage the edges of the digital signals). For custom builds with a longer ribbon cable to the LCD, the cable capacitance will add to the parasitic C of the LCD inputs, too. Maybe the 2k7 R* + the C_LCD_input + C_wires might be too much for faster SPI bit-bang at 20MHz sometimes (only a guess, I didn't test it).
Found it,
https://www.displayfuture.com/Display/datasheet/controller/ST7565.pdf the LCD pin capacity for mine is 8pF (page 59 of 72). Corner frequency will be about 7MHz, but to pass nice square edges through it, the bit-bang will gave to be about 10 times slower. I would expect problems if the equivalent bit-bang SPI clock goes higher than 500kHz.
Anyway, even without any series resistor, the current from an ATmega DO at 5V to a 3.3V+0.6V LCD input clamp diode probably won't be more than a mA or so but I didn't measure. A few mA will be safe to handle by any input clamp diodes the LCD might have on its inputs. My guess is, the real reason for no voltage level adapter is because the LCD inputs are in fact 5V tolerant (but at a first glance can't see 5V tolerant inputs mention in the datasheet, so it might not be).
- about the second C*/0.1uF at the AVCC (by the way, it's a good idea to always number or name any components on a schematic, so to easily refer to them later). As opposed to the 0.1uF near Vcc (where it is added to keep the fast current edges inside the MCU), the 0.1uF is to keep out any incoming spikes, so it will be more effective with a series ferrite bead, or a shunt L, or even a small resistor between the Vcc and the 0.1uF+AVCC, to form a low pass filter.
On the VCC pin, the MCU don't care much about outside noises, so the 0.1uF role is to minimize the escape of the internal RF produced spikes into outside, into the rest of the PCB. It keeps the inside MCU noises inside the MCU.
On the AVCC pin, the role of the 0.1uF is to keep the outside noises outside of the MCU, so to not influence the ADC and the other blocks sensitive to analog noise. In fact, the datasheet recommends a low pass filter, not just a decoupling 0.1uF. A ferrite bead, or a small R in series between the 5V and the 0.1uF at the AVCC should help even more.
Of course, these are generic comments, and I didn't try them in practice. They might not apply much when the manufacturer sources its BOM based on lowest price alone. So, if you observe better performance with the changes in red, definitely keep them.