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| 34410A ADC |
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| NNNI:
Hello, This might sound like a rather absurd request, so let me provide some context. I've been interested in integrating ADCs for over a year and have attempted to build my own, which you can find here: https://www.eevblog.com/forum/projects/(yet-another)-diy-multislope-adc I came across this rather interesting paragraph in the Art of Electronics (third edition) on page 921, detailing the operation of Agilent's Multislope IV topology: "Looking at Multislope IV waveforms with a scope, you see a much different beast. A1b has been replaced with a faster AD829 op-amp (120 MHz, 230 V/μs), with the integrating capacitor C1 reduced by 5×. A hardware engine forces the error integrator to produce consistent 10 Vpp ramps with a 2μs period, using coarse data from an 80MHz AD9283 converter digitizing the 10V ramp at 14 ns intervals, and fine data from an AD9200 10-bit converter with a limited 2V range, clocked at 75 ns intervals near zero volts. Slope changes and the counter record are made at 75 ns intervals, and the AD9200 makes starting and ending readouts with 0.02% resolution. As a result, a Multislope IV converter can measure 4.5 digits in 20μs (0.001 PLC), or 20× faster than Multislope III." I tried to figure out exactly what was going on here, but the description is somewhat vague and does not go into the details much. I was able to find a few relevant patents (US6876241 and US20050024119A1) and the schematic (https://www.dcddcc.com/blog/34410a/schematic.34410a.pdf), but once again, they don't particularly dip into the operation of the ADC itself. The only way to analyze it would be to actually probe the ADC itself, but since my means are very limited as a student, I was wondering if someone here has already captured integrator/control circuit waveforms or would be open to doing so. Regards, NNNI |
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