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A High-Performance Open Source Oscilloscope: development log & future ideas
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tom66:

--- Quote from: gf on November 30, 2020, 07:06:38 pm ---I'm wondering whats up with the 640 MSPS?
The AC specifications of the HMCAD1520 are only given up to 640 MSPS, but not for 1000.
And Max. Conversion Rate is specifed as 640 as well (1 ch).
When do the 1000 apply? Do they only apply in HMCAD1511 compatibility mode (8-bit)?

--- End quote ---

Yes, it's 1GSa/s in 8-bit mode, 640MSa/s in 12-bit and 160MSa/s in 14-bit mode.
IMO 14-bit mode is a bit useless but probably a consequence of the internal 14-bit core (which HMCAD1511 shares)
gf:
I guess you mean 105 MSa/s in precision mode, do you? (160 is obviously for 12-bit high speed @4ch)

I don't think that precicion mode is really useless.
The main point of precision mode are IMO not the 14 bits, but the following:


--- Quote ---the high speed modes all utilize interleaving to achieve high sampling speed. Quad channel mode interleaves 2 ADC branches, dual channel mode interleaves 4 ADC branches, while  single  channel  mode  interleave all 8 ADC branches. In precision mode interleaving is not required and each ADC channel uses one ADC branch only.
--- End quote ---

This eliminates interleaving spurs, leading to a significantly better SFDR and SINAD.

The cost is a maximum sampling rate of 105 MSa/s - but with all 4 channels enabled.
So with 4 channels enabled, the precision mode sampling rate is only by a factor ~1.5 lower than the 160 MSa/s for 12-bit 2-fold interleaved high speed mode. I find this trade-off not too bad.
tom66:

--- Quote from: gf on November 30, 2020, 09:26:06 pm ---I guess you mean 105 MSa/s in precision mode, do you? (160 is obviously for 12-bit high speed @4ch)
--- End quote ---

That's what I get for not double checking the datasheet and quoting from memory.


--- Quote from: gf on November 30, 2020, 09:26:06 pm ---
--- Quote ---the high speed modes all utilize interleaving to achieve high sampling speed. Quad channel mode interleaves 2 ADC branches, dual channel mode interleaves 4 ADC branches, while  single  channel  mode  interleave all 8 ADC branches. In precision mode interleaving is not required and each ADC channel uses one ADC branch only.
--- End quote ---

This eliminates interleaving spurs, leading to a significantly better SFDR and SINAD.

The cost is a maximum sampling rate of 105 MSa/s - but with all 4 channels enabled.
So with 4 channels enabled, the precision mode sampling rate is only by a factor ~1.5 lower than the 160 MSa/s for 12-bit 2-fold interleaved high speed mode. I find this trade-off not too bad.

--- End quote ---

OK, that's actually a really good point and one I didn't consider. Thanks! 
tom66:
Thanks for all the comments so far and for those who have filled out the survey.  For anyone who has missed it, please submit your response here:

https://docs.google.com/forms/d/e/1FAIpQLSdm2SbFhX6OJlB834qb0O49cqowHnKiu7BEsXmT3peX4otOIw/viewform

All responses are appreciated - I am looking to make an announcement in the new year regarding the direction of this project.
nctnico:

--- Quote from: tom66 on November 29, 2020, 06:49:24 pm ---It would of course be very interesting to see what you come up with nctnico.  In the meantime I am focused on the digital systems engineering parts of this project.  I am presently designing the render-acquisition engine which would replace the existing render engine in software on the Pi.

--- End quote ---
I'd advise against that. With the rendering engine fixed inside the FPGA you'll loose a lot of freedom in this part. Lecroy scopes do all their rendering in software to give them maximum flexibility for analysis. A better way would be to finalise the rendering in software first and then see what can be optimised where using the FPGA is the very very last resort. IMHO it would be a mistake to put the rendering inside the FPGA because it will fixate a lot of functionality and lock many people out of being able to help improve this design.
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