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A High-Performance Open Source Oscilloscope: development log & future ideas
nctnico:
You can seperate the FIFO if you create chunks of data. So the FIFO (and storage system) always works with a fixed size (say 256 bytes to 1024 bytes). In my design I even went a step further and used records which could contain various types of data (decimated, decoded, digital channels, different bit widths). These records (which could have different data rates!) where streaming into the memory from several FIFOs. The upside is that the memory doesn't need to care what part is for which channel but the downside is that you'll have to read all the data even if you are interested in a particular type of data (for example re-decode from channel 1) and there is some overhead but memory is cheap nowadays.
tom66:
The goal would be to have the data in linear planes so all ch1 data for a given acquisition would be in order, followed by ch2, ch3 and so on. I'm not too worried about where individual waveform groups are, but each channel should be in a separate plane. That way, when data is read out, it is in order (besides the need to rotate for pre-triggers.) In theory, I can then have another, say, 16-bit side channel for MSO functions, which is on ADC clock. (It would also be possible to do state analysis for MSO function using this, although it might be difficult to line that up with analog channels at that point.)
This is something I wanted to do a while ago, but the complexity put me off. But, I'm realising what a pain it is to have to deal with interlaced data when it comes to plotting data and processing it afterwards with filters and the like.
I think one of the biggest challenges to solve is memory arbitration, given one 64-bit AXI bus has 1.6GB/s peak bandwidth I'll need to appropriately arbitrate, possibly across two ports, to make this work well, to avoid running out of bandwidth as more time will be sent setting up smaller transactions.
rhb:
A mux/demux (serial/parallel) conversion at any point in a DSP pipeline is cheap to do and often both are done to optimize resource utilization in a gate level design.
If you are downsampling, which is the usual case, you have multiple fabric cycles available for each output sample. A 2x downsample allows two ops per cycle, 4x four ops, etc.
The writer only has to deal with the addressing once. The reader has to do it every time, so for efficiency the data need to be in reader optimal order.
Have Fun!
Reg
tom66:
Agreed. It's just down to getting that to work fast. There are plenty of ways to do this slowly - it's more difficult to do this when you need to process over a billion samples per second.
dougg:
Just in case this link is useful and you don't already know about it:
https://www.ti.com/tool/TIDA-00826
which is titled "50-Ohm 2-GHz Oscilloscope Front-end Reference Design". From the associated pdf the design definitely looks non-trivial.
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