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A High-Performance Open Source Oscilloscope: development log & future ideas
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nctnico:

--- Quote from: tom66 on February 09, 2021, 08:29:19 am ---In my original sketching of ideas I had always planned for an IC like LMH2832.
https://www.ti.com/lit/ds/symlink/lmh2832.pdf

This would be combined with a single -39dB attenuation relay to get you a 78dB attenuation range in total. 

--- End quote ---
The tricky part of VGAs in general is that they need differential inputs with a specific DC offset. Not impossible but it takes some careful planning. I'm also not convinced a VGA is the solution with the lowest noise. DSOs using the HMCAD1511 (without VGA) are consistently showing extremely low noise levels.


--- Quote ---If you want the precision modes of the ADC, you can't use the gain stages.  For 8-bit mode they may be sufficient.  Not sure if the gain stages vary with the '1511,  if it uses just an 8-bit core internally,  or if the true difference between the parts is only the ability to export that precision data out.

The HMCAD1511 also requires all of its inputs to be centred around VCOM, about 1 volt.  Shouldn't be a problem, just be aware it has a limited common mode range.

--- End quote ---
Don't worry, I have catered for a VCOM pin on my design.
gf:

--- Quote from: tom66 on February 09, 2021, 08:29:19 am ---Not sure if the gain stages vary with the '1511,  if it uses just an 8-bit core internally,  or if the true difference between the parts is only the ability to export that precision data out.

--- End quote ---

I'm pretty confident that it is the latter. The 1511 digital gain application notes I referenced above also mention higher internal precision. I guess the limitation is rather the maximum LVDS output data rate, which limits even the 1520 to 2/3 of the full sampling rate when it outputs 12-bit high-speed data instead of 8-bit.

14-bit precicsion mode of the 1520 is still a bit different, as it utilizes only single ADC core per analog channel w/o interleaving.
tom66:
If it was just data rate limit then the 640Msa/s 12-bit unpacked mode only uses ~7.7Gbit/s link rate, which is actually lower than the 8-bit 1GSa/s mode. 

I plan to use the part in a 16-bit padded mode as it's more compatible with a single receiver engine, just need to adjust how the data is unpacked (the SERDES blocks on a Xilinx 7 series part can't be dynamically resized).   This will limit sample rate to 500Msa/s on 12-bit mode.  Further work would be required to move the SERDES to a receiver with a gearbox that could interpret each 8-bit word received differently, which is needed to unlock the 640MSa/s rate (+28%). 

I suspect (if there is a difference at all, which I have yet to validate) that the '1511 has a fuse or laser disable for the additional functions that the '1520 has.  If we're really lucky there is no difference at all, just the '1520 functions in '1511 register space are unqualified and untested (a bit like the 40MSa/s ADC in the old Rigols that was running at 100MSa/s!)

Informally, with the basic on board PLL I have got the '1511 on one board up at 1.2Gsa/s, I suspect the PLL was the ultimate limit as the failure was a loss of lock for the ADC, as if the input amplitude requirement (which was already marginal) was being violated even at 1GSa/s due to my buggy PLL design.  I'll try with a higher amplitude or external clock sometime.
gf:

--- Quote from: tom66 ---If it was just data rate limit then the 640Msa/s 12-bit unpacked mode only uses ~7.7Gbit/s link rate, which is actually lower than the 8-bit 1GSa/s mode.

--- End quote ---
I think they wanted to avoid an odd number like 666.66666...GSa/s, and decided that 640 is a "nice" number which is close enough.
tom66:

--- Quote from: gf on February 09, 2021, 05:47:22 pm ---
--- Quote from: tom66 ---If it was just data rate limit then the 640Msa/s 12-bit unpacked mode only uses ~7.7Gbit/s link rate, which is actually lower than the 8-bit 1GSa/s mode.

--- End quote ---
I think they wanted to avoid an odd number like 666.66666...GSa/s, and decided that 640 is a "nice" number which is close enough.

--- End quote ---

Yes - but point is it's not the LVDS transceivers that limit that data rate.
It's either a difference in the ADC structures, or perhaps more likely just the better parts that are picked to have 12/14 bit modes with good enough INL/DNL/some other parameter?  There may not be any difference at all...
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