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A High-Performance Open Source Oscilloscope: development log & future ideas
gf:
--- Quote from: tom66 on February 09, 2021, 06:22:30 pm ---Yes - but point is it's not the LVDS transceivers that limit that data rate.
--- End quote ---
Given the specified 20%-80% LVDS clock an data rise and fall times of 0.7ns in the "LVDS Output Timing Characteristics" I don't see how the LVDS data rate can be significantly more than 1Gbit/s per lane, without violating these specs. At 1Gbit/s the data are stable for only 0.3ns, and at say 1.5 Gbit/s the data had no time to settle, given 0.7ns rise time. These specs apply to both 1511 and 1520. In practice the tranceivers may happen to be faster of course, but they don't guarantee it.
[ And if the data rate must not exceed 1Gbit/s per lane (by definition/specification) then the conversion rate needs to be reduced to <= 666MSa/s when 12 bits instead of 8 need to be transferred per conversion. ]
nctnico:
--- Quote from: gf on February 09, 2021, 07:54:27 pm ---
--- Quote from: tom66 on February 09, 2021, 06:22:30 pm ---Yes - but point is it's not the LVDS transceivers that limit that data rate.
--- End quote ---
Given the specified 20%-80% LVDS clock an data rise and fall times of 0.7ns in the "LVDS Output Timing Characteristics" I don't see how the LVDS data rate can be significantly more than 1Gbit/s per lane, without violating these specs. At 1Gbit/s the data are stable for only 0.3ns, and at say 1.5 Gbit/s the data had no time to settle, given 0.7ns rise time. These specs apply to both 1511 and 1520. In practice the tranceivers may happen to be faster of course, but they don't guarantee it.
--- End quote ---
It is differential! In the end it depends on the threshold of the receiver; the pulse width of the receiver will be the full cycle (minus some jitter). If you look at the datasheet there is an intentional 50ps delay between the LVDS clock output and data output as well.
gf:
--- Quote from: nctnico on February 09, 2021, 08:04:53 pm ---
--- Quote from: gf on February 09, 2021, 07:54:27 pm ---
--- Quote from: tom66 on February 09, 2021, 06:22:30 pm ---Yes - but point is it's not the LVDS transceivers that limit that data rate.
--- End quote ---
Given the specified 20%-80% LVDS clock an data rise and fall times of 0.7ns in the "LVDS Output Timing Characteristics" I don't see how the LVDS data rate can be significantly more than 1Gbit/s per lane, without violating these specs. At 1Gbit/s the data are stable for only 0.3ns, and at say 1.5 Gbit/s the data had no time to settle, given 0.7ns rise time. These specs apply to both 1511 and 1520. In practice the tranceivers may happen to be faster of course, but they don't guarantee it.
--- End quote ---
It is differential! In the end it depends on the threshold of the receiver; the pulse width of the receiver will be the full cycle (minus some jitter). If you look at the datasheet there is an intentional 50ps delay between the LVDS clock output and data output as well.
--- End quote ---
Sure, in the end it depends on the receiver threshold; and the programmable clock phase also enables adjusting the point in time where the clock crosses the receiver threshold. But even if it still happens to work I would no longer call it a "clean" timing when the transition time exceeds the unit interval. And LVDS standards are obviously even stricter.
https://www.ti.com/lit/ug/slld009/slld009.pdf?ts=1612860014236
--- Quote ---LVDS/M-LVDS Summary
The most attractive features of LVDS include its high signaling rate, low power consumption, andelectromagnetic compatibility. The following sections summarize each of these benefits and Chapter 2, LVDSand M-LVDS Line Circuit Characteristics and Features, offers a more detailed explanation.Signaling RateWe define the number of state changes per unit time as the signaling rate for the interface. Knowing the unitinterval time, tUI, between state changes, you can derive the signaling rate as the inverse of the unit interval.TIA/EIA-644-A and TIA/EIA-899 require that driver output transition times be less than 30% of the unit interval,with a lower limit of 260 ps and 1 ns, respectively. The standards also recommend that the transition time atthe receiver input be less than 50% of the unit interval. The difference between driver output rise time andreceiver input rise time allows for signal degradation through the interconnect media
--- End quote ---
tom66:
Well, for what it is worth, the standard speed grade of the Zynq is only rated to 950Mbit/s per pin on SERDES and I haven't yet got the input delay tuning algorithm working, but it works stable whether hot or cold. On this basis (though, admittedly with no way to measure it) I suspect the LVDS signal is not as marginal as suggested and the specifications are worst case, though I may have just gotten lucky!
nctnico:
--- Quote from: gf on February 09, 2021, 10:01:45 pm ---
--- Quote from: nctnico on February 09, 2021, 08:04:53 pm ---
--- Quote from: gf on February 09, 2021, 07:54:27 pm ---
--- Quote from: tom66 on February 09, 2021, 06:22:30 pm ---Yes - but point is it's not the LVDS transceivers that limit that data rate.
--- End quote ---
Given the specified 20%-80% LVDS clock an data rise and fall times of 0.7ns in the "LVDS Output Timing Characteristics" I don't see how the LVDS data rate can be significantly more than 1Gbit/s per lane, without violating these specs. At 1Gbit/s the data are stable for only 0.3ns, and at say 1.5 Gbit/s the data had no time to settle, given 0.7ns rise time. These specs apply to both 1511 and 1520. In practice the tranceivers may happen to be faster of course, but they don't guarantee it.
--- End quote ---
It is differential! In the end it depends on the threshold of the receiver; the pulse width of the receiver will be the full cycle (minus some jitter). If you look at the datasheet there is an intentional 50ps delay between the LVDS clock output and data output as well.
--- End quote ---
Sure, in the end it depends on the receiver threshold; and the programmable clock phase also enables adjusting the point in time where the clock crosses the receiver threshold. But even if it still happens to work I would no longer call it a "clean" timing when the transition time exceeds the unit interval. And LVDS standards are obviously even stricter.
https://www.ti.com/lit/ug/slld009/slld009.pdf?ts=1612860014236
--- Quote ---LVDS/M-LVDS Summary
The most attractive features of LVDS include its high signaling rate, low power consumption, andelectromagnetic compatibility. The following sections summarize each of these benefits and Chapter 2, LVDSand M-LVDS Line Circuit Characteristics and Features, offers a more detailed explanation.Signaling RateWe define the number of state changes per unit time as the signaling rate for the interface. Knowing the unitinterval time, tUI, between state changes, you can derive the signaling rate as the inverse of the unit interval.TIA/EIA-644-A and TIA/EIA-899 require that driver output transition times be less than 30% of the unit interval,with a lower limit of 260 ps and 1 ns, respectively. The standards also recommend that the transition time atthe receiver input be less than 50% of the unit interval. The difference between driver output rise time andreceiver input rise time allows for signal degradation through the interconnect media
--- End quote ---
--- End quote ---
Yes and no. The steeper the edges the more noise & heat dissipation (which is what a high speed / precission ADC can do without). Slower edges means more jitter at the receiver's end but since the connection between the ADC and FPGA is basically a synchronous parallel bus over a distance of a few cm at most, the environment is much better defined. The TI document is about using LVDS in multi-drop situations over relatively long distances and likely in a way where the receiver also needs to do clock recovery where jitter could be an issue.
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