Following on from nctnico's advice, are you sure clock and data are the right way around? It looks like it may be continually seeing start states as the bus decode is switching mid-byte.
Edit: I am sure nctnico is right, your SCL trigger level on channel 1 is at ground for example: you adjust the thresholds by adjusting thr trigger level when using analogue channels for I2C decode when selecting the channel for SCL, and then the same when you select the SDA channel.