http://www.agm-micro.com/products.aspx?lang=&id=3113&p=37
MCU frequency 248Mhz
SRAM 128Kbytes
This is where things get just a little uncertain.
Version 1.0 of the Data Sheet says that the Maximum Speed of the AG32VF303 is 208 MHz. Only the AG32VF407 gets 248 MHz. All other versions are even lower speed.
Version 1.2 of the Reference Manual gives the maximum speed of all versions as 248 MHz! Why the difference? Which one is correct?
Assuming that the 248 MHz is correct, then running at 250 MHz is not a big deal. It just gives the manufacturer an excuse to not support you if it doesn't work.
So are we sure that 248Mhz is not enough?
It's difficult to answer that question. The 248 MHz is just a clock on the chip. It doesn't tell you how long any particular operation takes. You need extra information for that, which doesn't appear in the Data Sheet nor the Reference Manual. Any particular operation might take more than on clock cycle.
Assuming that these chips use just one cycle for any (or almost all) operations. Then that would imply that the RAM should be able to get written to at a 250 MHz rate.
That just leaves a few more questions, including:
Are the general purpose I/O pins capable of handling data at a 250 MHz rate?
Where is the comparator to handle triggering? The DMA subsystem doesn't appear to have one.
Is the FPGA user-programmable?
Scanning though the manuals, I couldn't find an answer to these questions. Perhaps there are other manuals available?
I can't say that the chip is capable of performing the required function, but nor can I rule it out.
Because rough calculation ( not sure if correct ) would be
We need 250MSps. (It's for both channels of ADC together. It should be enough for both channels at 60Mhz or one channel at 120Mhz as they mention in their specs.)
1 Sample => 8 bits = 1Byte
If we take 2 samples at a particular time ( either for both channels or one channel using both channels of ADC )
Theoretically we can
2 Bytes * 248 Mhz => 496MBps using half of the bandwidth of the memory
I am not sure how many CPU cycles writing into the internal memory takes. Or if any at all, because they mention DMA access.
But it looks like it should be enough. I am just a total beginner, to maybe this calculation is all wrong.
You certainly could ease the speed problem by gathering multiple bytes and feeding them as a block to the chip. However, that means that you need extra logic external to the chip (registers and sequencing logic). I see no evidence of that logic on the circuit board. EDIT: I now see that you don't need these separate registers, etc. All you need is a dual ADC, and when you look at the board photos, this seems to be the case. I don't know what the actual ADC is, but the pinout looks similar to an AD9288, as shown in this annotated detail: