Products > Test Equipment
Anritsu MS2721B internal CF card missing
analogRF:
--- Quote from: brainstorm on October 06, 2021, 01:24:02 pm ---JTAG for the SuperH4 processor identified and mapped out. Will connect a probe there next and try to enumerate/halt :)
--- End quote ---
great work :)
I just hope the debug interface is not disabled. Or at least if it is disabled, it can be enabled by moving some pull-up/down resistors on the board that can be identified (like in Keysight 3000A scopes)
by the way, can I ask how you identified the pins? just by tracing to the CPU pins?
I always suspected that empty pin header but never really dug into it...a lot of things now can be done through jtag ;) ;)
analogRF:
still a UART debug console would have been more useful at this point for troubleshooting but Jtag can also be useful to some extent
did you check for any UART port? such as P4000 pin header? or specially J5001 right next to the jtag header?
brainstorm:
--- Quote from: analogRF on October 06, 2021, 01:29:02 pm ---
--- Quote from: brainstorm on October 06, 2021, 01:24:02 pm ---JTAG for the SuperH4 processor identified and mapped out. Will connect a probe there next and try to enumerate/halt :)
--- End quote ---
great work :)
I just hope the debug interface is not disabled. Or at least if it is disabled, it can be enabled by moving some pull-up/down resistors on the board that can be identified (like in Keysight 3000A scopes)
by the way, can I ask how you identified the pins? just by tracing to the CPU pins?
I always suspected that empty pin header but never really dug into it...a lot of things now can be done through jtag ;) ;)
--- End quote ---
Thanks! Just good old DMM continuity test and datasheet (page 11 of 1074): https://datasheet.octopart.com/HD6417750F167V-Renesas-datasheet-11770390.pdf
Also the GND row was an immediate giveaway, all JTAG connectors seem to have that ground row to interleave with the signals for better signal integrity and avoid coupling.
I'm a bit concerned about its real utility though since there's that weird non-JTAG signal (ASEBRK/BRKACK) from Renesas H-UDI proprietary (debug) protocol (https://www.farnell.com/datasheets/1513948.pdf)... in the datasheet they say that they implement a "subset of the IEEE 1149.1 JTAG standard" but in renesasrulz.com there are empty threads of users not able to operate the JTAG at all (as it was normal/standard JTAG), we shall see... if you have a $1500 E10A-USB or E20 "emulator" Renesas probe, can you connect it there and let me know? ;)
Thanks for the hint of the serial header on P4000, I'll definitely poke that too!
By J5001 I guess you mean J50014? I suspect that's a superset of the JTAG connector that supports these Lauterbach probes?: https://www.lauterbach.com/frames.html?pro/pro_sh7047f_alt01.php
analogRF:
i am not an expert on this matter but I dont think you need the Renesas emulator. Segger J-Link that I do my jtags with and is excellent, does support this cpu here and I dont think that extra pin needs connecting...
brainstorm:
--- Quote from: analogRF on October 06, 2021, 09:38:09 pm ---i am not an expert on this matter but I dont think you need the Renesas emulator. Segger J-Link that I do my jtags with and is excellent, does support this cpu here and I dont think that extra pin needs connecting...
--- End quote ---
Yeah, that's my hope, I have a Glasgow interface explorer, which should do for this usecase... I just probed the P4000 header with the oscilloscope, but I couldn't find any trace of serial activity or any waveform, just high at 3.3V on all the pins (except one GND). No activity during powerup/bootloop in any of the pins, I suspect that it's too early in the boot process and not even the UART is initialized yet :-S
Could you please put your oscope probe there and let me know if you see anything?
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