Products > Test Equipment
RD JDS6600 25MHz 2-Channel DDS AW Function Signal Generator
pantelei4:
--- Quote from: Enoch on July 25, 2017, 02:48:23 am ---I received my JDS6600 yesterday, phase tracking no problem. :scared:
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Turn on infinite persistence And tuning of frequencies.
When the frequency is tuned, the synchronized second channel loses the phase randomly.
RD Tech:
--- Quote from: pantelei4 on July 24, 2017, 10:19:31 am ---
--- Quote from: Kleinstein on July 24, 2017, 08:53:29 am ---The jitter should not depend on the H/L ratio. It should be just a question of the 5 ns time raster. So it depends on the frequency too. This might even be the worst aspect of it. At frequencies that don't have a period that is an integer multiple of 5 ns will show the jitter. So more like low jitter only at a few special good frequencies.
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This generator does not have jitter at non-multiple frequencies, unlike other budget DDS.
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at square wave, our wave is not jitter . this is my advantage. so you have JDS6600, you can check
RD Tech:
--- Quote from: Kleinstein on July 24, 2017, 08:53:29 am ---The jitter should not depend on the H/L ratio. It should be just a question of the 5 ns time raster. So it depends on the frequency too. This might even be the worst aspect of it. At frequencies that don't have a period that is an integer multiple of 5 ns will show the jitter. So more like low jitter only at a few special good frequencies.
Depending on how frequency calibration is done the good frequencies can be slightly different, depending on the exact quartz frequency. In principle they could use a different frequency scale - allowing only good ones (e.g. divider) and maybe warn about poor ones.
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yes, that is a standar too to judage a DDS
RD Tech:
--- Quote from: Kleinstein on July 21, 2017, 08:59:05 am ---A special DAC chip is generally better than using just a resistor chain at the FPGA output. Most DACs do not offer that much of isolation between the digital side and analog output. So noise is in both cases a question of a good layout. This is still a low cost generator - so the cheap resistor ladder DAC is a kind of compromise.
The failure is to label it 14 Bit resolution if they actually only get 11 Bits.
The Resistor chain looks like 8 Bit R2R and 14 or 15 resistors thermometer style. So at best they could get something like 12 Bit resolution. Still I am surprised how good it seemed to work. If not careful, even at 8 Bits R2R one can get significant errors. One sees that with other low cost generators that call for 8 or 12 Bit resolution and only deliver 6-7. With an actual 11 Bit resolution it is already a big step forward.
Using true 14 or maybe just 12 Bit DACs is a cost factor - though they might save on the amplitude control this way.
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About a resistor chain at the FPGA output, I have explain, and your explain is good and right too , for any plan, it was designed better , it will all be good.
about the bit, I don't why where you find, because we write 12 bit Waveform vertical resolution , not 14bit.
about the 14 bit , we have updated, but we only sell at china for now. because we need to test in china, after test, and no one find the problem, so we sell to the world. it is our rule for publishing the products. all our products have this progress.
thank you for your support again
pantelei4:
--- Quote from: RD Tech on July 25, 2017, 06:19:21 am --- we have updated, but we only sell at china for now. because we need to test in china, after test, and no one find the problem, so we sell to the world. it is our rule for publishing the products. all our products have this progress.
thank you for your support again
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Why then I received an imperfect product? |O
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