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| Building my own scope |
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| balnazzar:
--- Quote from: pcprogrammer on October 21, 2022, 05:29:31 am ---There is one thing that is overlooked in this talk about a scope without a FPGA, and that is DMA. (direct memory access) It is possible to do sustained capture with it, but to do triggering on the signal will still require the processor to do a lot of work. With microcontrollers it still would not bring the high sample rates. No idea about the speeds that can be obtained with a modern PC. The cards of the company found by you, balnazzar (https://dev.alazartech.com/en/) also uses a FPGA and has lots of memory on the card to do the data capture. As a starting point for learning take a look here: https://www.fpga4fun.com/digitalscope.html It starts with the basics. Since you, balnazzar, did not comment on my last post it might be that you missed it. It provides lots of information you asked for. https://www.eevblog.com/forum/testgear/building-my-own-scope/msg4474414/#msg4474414 --- End quote --- Thanks, quite informative. I indeed missed it, or I owuld have at least thanked you for it! :) Also I didn't catch that alazartech cards had a FPGA.. BAsically then, they are quasi-whole oscilloscopes, except they are directly inserted into the pcie slot rather than using usb or thunderbolt.. I thought they were just analog front end plus ADCs.. Once more, thanks. |
| tggzzz:
--- Quote from: balnazzar on October 21, 2022, 10:01:01 am --- --- Quote from: gf on October 21, 2022, 05:17:07 am ---The low-cost Hantek 6022BE uses an EZ-USB microcontroller to stream the ADC samples via USB2 to the PC. No FPGA involved. Sample rate is 48MSa/s, IIRC. Processing (incl. trigger) is done on the PC. --- End quote --- If 48 MSa/s is the best one can do without FPGA, then FPGA is necessary. --- End quote --- Not if you are only interested in audio signals :) (But for audio you might to be very interested in the dynamic range and linearity, for which a decent sound card could be a good "front end + ADC".) |
| gf:
--- Quote from: balnazzar on October 21, 2022, 10:01:01 am --- --- Quote from: gf on October 21, 2022, 05:17:07 am ---The low-cost Hantek 6022BE uses an EZ-USB microcontroller to stream the ADC samples via USB2 to the PC. No FPGA involved. Sample rate is 48MSa/s, IIRC. Processing (incl. trigger) is done on the PC. --- End quote --- If 48 MSa/s is the best one can do without FPGA, then FPGA is necessary. --- End quote --- I think 48 MSa/s was chosen due to USB2 speed limit, and due to the EZ-USB FX2 clock frequency, from which the ADC clock is directly derived as well. In the mean time there also exist EZ-USB FX3 controllers for USB3. I guess they would enable a higher rate. Yet another limit is of course the processing speed of a PC. |
| pcprogrammer:
High speed with 8 or more bits per sample results in high bit rates. 1 channel at 1 GSa/s for 8 bits per sample means 8Gbps, which is more then USB3 can handle. Even for a FPGA it is fast unless paralleling is used. The ADC used in the Hantek DSO2000 series uses a multi phase clock to bring the speed down and spread it over 4 separate bytes into the FPGA. To write it into memory this is also needed. Clocks and data signals at higher rates bring a bucket load of problems that yo need to be aware of. High speed FPGA design is also tricky. I'm learning about this at the moment and it is not like just slapping some gates together and you got something running. It requires timing constraints and tweaking to get a proper design. For learning my advice is to stick to sample rates below 100Msa/s. |
| Fungus:
--- Quote from: alm on October 21, 2022, 08:58:46 am ---There's always the possibility to do triggering in the analog domain using a fast comparator and timer. That would remove the need to do any real time calculations on the data. --- End quote --- A simple rising/falling edge trigger can probably be done on a PC in software. Modern DSOs can do far more than that though. Take a look at the trigger menu of the average 'scope these days, there's runt pulses, zones, serial data... all stuff that needs an FPGA. |
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