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| Building my own scope |
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| rob77:
--- Quote from: tggzzz on October 21, 2022, 09:51:22 am --- --- Quote from: rob77 on October 20, 2022, 11:58:07 pm --- --- Quote from: tggzzz on October 20, 2022, 11:19:49 pm ---Probably, but omit the FPGA and have a FIFO that isn't tied to a communication device ;) Cats? I know lots of ways to skin them ;D --- End quote --- and how exactly would you connect it to the computer ? --- End quote --- Sigh. Why do people choose to omit context relevant to their point? Here's what I was replying to... --- Quote from: rob77 on October 20, 2022, 10:17:18 pm ---isn't that exactly what the FPGA + USB fifo + OS device driver combo does ? ;) --- End quote --- Don't use the "USB fifo" as part of the scope's functionality. --- End quote --- it's pretty relevant i think.. if you propose a solution it must be something that can be implemented in real life.. if your proposed solution mentions "computer will read the fifo" then please share your idea how... probably you didn't noticed that nowadays computers have only PCIe , USB, LPC , SPI, SMBUS I2C.... nothing else , have a look at the datasheets of the CPUs used in computers, for high speed it's PCIe and USB , for generic peripherals it's a superio chip connected through LPC , bios and sensors is SPI, i2c, smbus..... and it's like that for at least a decade... there is no other way to interface a computer, and only the first 2 in the list are fast enough for data capture at reasonable rates for a scope. |
| 2N3055:
--- Quote from: Fungus on October 21, 2022, 11:20:42 am --- --- Quote from: alm on October 21, 2022, 08:58:46 am ---There's always the possibility to do triggering in the analog domain using a fast comparator and timer. That would remove the need to do any real time calculations on the data. --- End quote --- A simple rising/falling edge trigger can probably be done on a PC in software. Modern DSOs can do far more than that though. Take a look at the trigger menu of the average 'scope these days, there's runt pulses, zones, serial data... all stuff that needs an FPGA. --- End quote --- At what sample rate you think that can be made? How much data can be synchronously transfered to PC per second without loosing a single bit....? |
| tggzzz:
--- Quote from: rob77 on October 21, 2022, 09:51:06 pm --- --- Quote from: tggzzz on October 21, 2022, 09:51:22 am --- --- Quote from: rob77 on October 20, 2022, 11:58:07 pm --- --- Quote from: tggzzz on October 20, 2022, 11:19:49 pm ---Probably, but omit the FPGA and have a FIFO that isn't tied to a communication device ;) Cats? I know lots of ways to skin them ;D --- End quote --- and how exactly would you connect it to the computer ? --- End quote --- Sigh. Why do people choose to omit context relevant to their point? Here's what I was replying to... --- Quote from: rob77 on October 20, 2022, 10:17:18 pm ---isn't that exactly what the FPGA + USB fifo + OS device driver combo does ? ;) --- End quote --- Don't use the "USB fifo" as part of the scope's functionality. --- End quote --- it's pretty relevant i think.. if you propose a solution it must be something that can be implemented in real life.. if your proposed solution mentions "computer will read the fifo" then please share your idea how... probably you didn't noticed that nowadays computers have only PCIe , USB, LPC , SPI, SMBUS I2C.... nothing else , have a look at the datasheets of the CPUs used in computers, for high speed it's PCIe and USB , for generic peripherals it's a superio chip connected through LPC , bios and sensors is SPI, i2c, smbus..... and it's like that for at least a decade... there is no other way to interface a computer, and only the first 2 in the list are fast enough for data capture at reasonable rates for a scope. --- End quote --- I think there is a language problem here; I'm not sure what you are arguing against and for. I am guessing English isn't your first language. You wrote "the FPGA + USB fifo + OS device driver combo" which could be parsed as "the (FPGA + USB) (fifo + OS device driver) combo" or "the FPGA + (USB fifo) + (OS device driver) combo". Only the latter makes some sort of sense, so that is how I interpreted it. Now a scope (of the type being discussed) will have a signal chain consisting of * analogue front end * ADC * data capture FIFO controlled by an FPGA or by other means * first level processing and control * communications mechanism to and from... * control and display GUI in a computerThe communications mechanism (5) could be over USB, Ethernet, SPI, UART, or even RFC1149 (or revision RFC2549). If you are using USB or Ethernet there will be one or more FIFOs in the comms mechanisms - as you noted. But, unless you wish to grossly simplify the hardware and limit performance, the FIFO in (5) is separate to the FIFO in (2). |
| Fungus:
--- Quote from: 2N3055 on October 21, 2022, 10:01:23 pm ---At what sample rate you think that can be made? --- End quote --- If I'm programming it on a multi-core 3GHz CPU with SSE instructions? Quite high... |
| rob77:
--- Quote from: tggzzz on October 21, 2022, 10:24:56 pm --- --- Quote from: rob77 on October 21, 2022, 09:51:06 pm --- --- Quote from: tggzzz on October 21, 2022, 09:51:22 am --- --- Quote from: rob77 on October 20, 2022, 11:58:07 pm --- --- Quote from: tggzzz on October 20, 2022, 11:19:49 pm ---Probably, but omit the FPGA and have a FIFO that isn't tied to a communication device ;) Cats? I know lots of ways to skin them ;D --- End quote --- and how exactly would you connect it to the computer ? --- End quote --- Sigh. Why do people choose to omit context relevant to their point? Here's what I was replying to... --- Quote from: rob77 on October 20, 2022, 10:17:18 pm ---isn't that exactly what the FPGA + USB fifo + OS device driver combo does ? ;) --- End quote --- Don't use the "USB fifo" as part of the scope's functionality. --- End quote --- it's pretty relevant i think.. if you propose a solution it must be something that can be implemented in real life.. if your proposed solution mentions "computer will read the fifo" then please share your idea how... probably you didn't noticed that nowadays computers have only PCIe , USB, LPC , SPI, SMBUS I2C.... nothing else , have a look at the datasheets of the CPUs used in computers, for high speed it's PCIe and USB , for generic peripherals it's a superio chip connected through LPC , bios and sensors is SPI, i2c, smbus..... and it's like that for at least a decade... there is no other way to interface a computer, and only the first 2 in the list are fast enough for data capture at reasonable rates for a scope. --- End quote --- I think there is a language problem here; I'm not sure what you are arguing against and for. I am guessing English isn't your first language. You wrote "the FPGA + USB fifo + OS device driver combo" which could be parsed as "the (FPGA + USB) (fifo + OS device driver) combo" or "the FPGA + (USB fifo) + (OS device driver) combo". Only the latter makes some sort of sense, so that is how I interpreted it. Now a scope (of the type being discussed) will have a signal chain consisting of * analogue front end * ADC * data capture FIFO controlled by an FPGA or by other means * first level processing and control * communications mechanism to and from... * control and display GUI in a computerThe communications mechanism (5) could be over USB, Ethernet, SPI, UART, or even RFC1149 (or revision RFC2549). If you are using USB or Ethernet there will be one or more FIFOs in the comms mechanisms - as you noted. But, unless you wish to grossly simplify the hardware and limit performance, the FIFO in (5) is separate to the FIFO in (2). --- End quote --- the whole point was to grossly simply the hardware and do all processing in software on the computer... i think it was pretty obvious from my posts.... same approach as you do with SDR - "simple" HW sending IQ data to the computer and gnuradio (or whatever else) doing the heavy lifting. and regarding the interfaces, everything you listed boils down to the very interfaces the CPU has (serial through superio on LPC, MAC controller connected to PCIe for ethernet...etc...) , so to get lowest latency and highest throughput you need to use one of those interfaces the CPU has implemented directly... and that's PCIe or USB. |
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