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Cheap and Small Dynamic Signal Analyzer?

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TopQuark:
https://www.eevblog.com/forum/testgear/siglent-sds2000x-hd-12bit-(published-for-chinese-domestic-market-only)/msg4489057/#msg4489057
Gave the DSA bode plot method a shot with my 12-bit scope, wrote a bit of software to try out the method. In my experiments noise seems to work best, as my function gen can't produce burst sweep chirp with 0v on either end, it is either continuous sweep or burst at fixed frequency. 

I currently have 3 directions I can pursue for the DSA project.

1. Go for the AD4630-2. Two channel 2 Msps @ 24 bits will make for a really high dynamic range DSA under 1MHz. Need to design my own breakout board, but chips is on the way. Sampling rate is low enough that a MCU might be good enough, might not need FPGA.

2. Go for ADC3683EVM. Two channel 65 Msps @ 18 bits. Good dynamic range, can look at signal under 30MHz and oversample for lower frequencies. Plug and play FMC card. Firmly in FPGA territory. I have a board on the way, might use it for the DSA project, or use it elsewhere.

3. Red pitaya. 125 Msps @ 14 bits. Can swap the ADC chip to LTC2185 for 16 bits and improve SNR by 3-4dB. I already have the board, everything is wired up well, DAC included. FPGA on board.

For my DSA needs, I only need to look at signal under 1MHz. But if I am to spend the trouble and effort to develop the project, I would want to have it work as a bode plot machine as well, and so I would want to have it work up to 10MHz. So currently I am leaning towards options 2 and 3.

TopQuark:
Look what arrived in the mail today  >:D

The ZU15EG FPGA SoC probably has more horsepower than most entry level scopes, and the ADC3683 is one hell of an ADC. Not cheap, nor small, but at least the hardware has the potential of being a kickass DSA.

KE5FX:
Cool ADC, but wow, what a brain-damaged clocking architecture.  If I'm reading the data sheet right, the LVDS output is synchronous to the sampling clock, but you have to supply the clock.  Oh, yes, and it has to run at rates like 4.5x SCLK in some of the more useful modes.  :wtf: 

If they hadn't bungled the digital side so badly, that chip wouldn't even need an FPGA.

TopQuark:
Yea it is pretty silly. Current thinking is to clock the ADC sampling clock input with a low jitter source. Data frame clock output (same freq as sampling clock, with delay and likely more jitter) from the ADC will be used to sync the data frame transfer and create the bit timing clock with a PLL on the FPGA.


 

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