Digital Oscilloscope

[Sebeom]

Hello,

I  have a plan to design a digital oscilloscope. The ADC sampling rate is 5GSPS. We will get the ADC data using FPGA. We need higher sampling rate for high-end oscilloscope. So we consider the ETS(Equivalent Time Sampling). In case of random ETS, we need to know the time of ADC clock rising edge after trigger event using TDC(Time to Digital Converter). I think this job is very challenging because TDC time resolution need to be around 10ps. Is there anyone who has a good idea to implement the higher sampling rate using the other method?

Thanks, Sebeom