Products > Test Equipment
DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
FrancisM:
Hello,
I wanted to test my LA at a higher frequency than those I use it most the time. 100MHz was the target, it's the fastest I can reach with the trough hole PICs at my disposal. I mounted a dsPic33EP in a dead bug style and overclocked it at 100MIPS, way over the 70MIPS given in the datasheet. I never tried it before but it works, at the expense of a jitter of around 900ps.
I used some cheap SDK08 grabbers I got recently. Looking nice but one has been badly mounted and is only usable on big pins, not smd. The hooks don't retract enough. Another one went electrically open during testing while ok mechanically. You get what you pay for.
I first tested at 50MIPS with different patterns for a maximal loading on all the lines. It was all good.
At 100MIPS, only the single walking bit was fine. The scope didn't even trigger on the other patterns. A single trig revealed a lot of crosstalk everywhere. The cure was to add a third ground line between each POD and the DUT.
I will probably never use the analyser at this speed, it's just good to know it behaves well.
Francis
oz2cpu:
wow FrancisM, thanks for the curves,
but dont you think the jitter is due to your software ?
and the way you trig ?
is it assembly ?
any conditional jumps ?
counters ?
it looks clearly like your code is not taking exactly the same time, each time thru
even a counter and a compare, will do that.
FrancisM:
Hi oz2cpu,
The jitter comes clearly from the PIC. It's for a reason Microchip gives an upper limit of 70MIPS for this chip. At this frequency, the output pulses are clean. At 74MIPS, the jitter starts to appear and the higher I go, the more I get.
I tried to clock the PIC with the AWG of the scope. This setup allows a max 25MIPS without using the PLL and it gives a perfect result. Single rising and falling edge on all digital lines. As soon as I engage the PLL and rise it's frequency, things worsen. My PIC is the limit and I knew it from the start. I have actually no other gear to provide 10ns pulses or less on 16 output lines.
The program is assembler and it's my first one on dsPIC. I made it to have no dead time between pulses, linear programing, no interrupts, just one inconditional branch to loop and this one takes three cycles, incredible.
The most important thing I learned is to have enough ground paths on each POD.
I'm pleased with the result and can be confident with everything I will do with this gear.
Thanks for the good job Thomas.
Francis
oz2cpu:
thanks for the uptate,
yes clearly a way to go with assembler,
looks like your pulses are very well designed,
it would be impossible to make them this clean with C
so what you say is : the jitter come from the overclocking = instabilities revealed just before total fail, near the max point.
very interesting observation, the methode is easy to recreate and idea can be reused to find the near max
of other devices.
FrancisM:
I tried to test how far the PIC could go without any output loading. It stopped working at 113MIPS with DC on the output I was monitoring.
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