Designing a DIY MSO probe for the Siglent SDS2000X Plus series: the theoryThe SDS2000X Plus oscilloscopes can show sixteen logic channels next to their analog traces, but only through Siglent's SPL2016 logic probe. Several people have built their own probe instead, and the EEVblog forum holds a long and generous thread on how. This article is not a build guide. It explains the electrical ideas behind such a probe: what the scope expects at its logic input, why the tip carries a resistive divider of about 11:1, how that divider is compensated, what the cable does at nanosecond timescales, and how to check the result with nothing but the scope.
Along the way it compares the author's design with two published community designs, and it points out one tempting addition, a resistor to ground at the scope end, that looks like good practice and quietly halves every threshold on the screen.
(The photo, Figure 1, is attached at the bottom of this post.)Figure 1. The author's probe on an SDS2104X Plus: 3M twisted-pair flat cable, 3D-printed plug shell and two eight-channel pods, with D0 on the 1 kHz calibrator.
1. What the scope expects from its probeThe models in the SDS2000X Plus series, from 100 MHz to 500 MHz, share the same logic-analyzer input and the same SPL2016 probe. The author's measurements were made on an SDS2104X Plus. Any of them turns into a 16-channel mixed-signal oscilloscope when a logic probe is plugged into the slot marked D0–D15 on the front panel. The slot is mechanically a PCIe x1 edge connector, but electrically it has nothing to do with PCI Express: 16 signal pins, each flanked by ground pins, feed 16 comparators inside the scope.
Siglent's own probe, the SPL2016, is specified as:
| Parameter | SPL2016 |
| Input impedance at the tip | 100 kΩ ‖ ~18 pF |
| Input dynamic range | ±20 V |
| Threshold range | ±10 V, 10 mV steps |
| Threshold presets | TTL 1.5 V, CMOS 2.5 V, LVCMOS 3.3 V (1.65 V), LVCMOS 2.5 V (1.25 V) |
| Minimum input swing | 800 mVpp |
| Maximum data rate | 300 Mbit/s |
| Threshold groups | D0–D7 and D8–D15 |
The numbers that matter for a DIY design are not printed there, because they are properties of the scope, not of the probe:
1.
The thresholds you set are tip voltages. The comparators never see 1.65 V; they see about an eleventh of it. The firmware scales your threshold setting down by the ratio of Siglent's probe before it programs the comparator reference. A home-made probe therefore has to divide by the same ratio, or every threshold on the screen is wrong by the same factor.
2.
The scope supplies part of the divider. A genuine SPL2016 measures 91.1 kΩ from tip to edge connector (tautech, EEVblog). Measured into the scope's LA pins, the input is about 9 kΩ to ground: the author reads 9.11 kΩ on a powered SDS2104X Plus with a Fluke 179, mawyatt measured ~8.6 kΩ with a resistive divider, and OZ2CPU's trimming implies ~9.6 kΩ. 91 kΩ over ~9.1 kΩ is a divider of about 11:1, and the sum is the datasheet's 100 kΩ. The ratio is usually called 10:1 by habit, but with the bottom leg inside the scope the arithmetic gives 11:1, and that appears to be what Siglent's own probe does too. It looks very much as if Siglent's 90.9 kΩ / 9.09 kΩ pair is split between the probe and the instrument. The bottom leg of the divider lives inside the oscilloscope.
3.
The comparators have hysteresis. DL2XY reports roughly 650 mV of hysteresis referred to the tip. That is generous, and it is why a correctly divided probe hardly ever chatters on slow edges, but it also means "the threshold" is really a band 0.65 V wide centred on the setting.
The rest of the design follows from these three facts.
2. Why attenuate at the tip at allA logic probe could in principle be a bundle of wires straight to the comparators. Every serious logic-analyzer probe since the 1980s has instead put a large resistor right at the tip, and the reasons still apply:
- Loading. A comparator input with its protection network is a few kΩ and several pF. Hung directly on an I²C line with 4.7 kΩ pull-ups, or on the output of a weak oscillator, that load changes the circuit you are trying to observe. 100 kΩ at the tip is loading an engineer can ignore in most digital circuits.
- Overvoltage. With ~91 kΩ in series, a tip accidentally touching 24 V or a gate-driver rail delivers a fraction of a milliamp into the protection diodes. Without it, the same slip drives the scope's ESD structures directly.
- Range and resolution. The comparator reference covers a little under ±1 V. Scaled up by the probe's ratio, that becomes the useful ±10 V threshold range on the screen, with 10 mV steps at the tip.
- Capacitance. The tip resistor is bridged by a small capacitor (5.6 pF in the author's probe, 8.2 pF in the classic HP-derived designs). Seen from the circuit under test, the probe is then that few pF in series with everything behind it, rather than the whole cable. That only works if the divider is compensated, which is the next topic.
3. Compensation: the same rule as a ×10 scope probeA resistive divider with stray capacitance on its bottom leg is a low-pass filter with a time constant in the hundreds of nanoseconds, which is useless for logic signals. The cure is the one every ×10 passive probe uses: bridge the top resistor with a capacitor so that the divider is capacitive at high frequency and resistive at low frequency, and choose the capacitor so that both ratios are the same.
The divider is flat (frequency independent) when
R_top · C_top = R_bot · C_bot
Put numbers on it. With 90.9 kΩ and 5.6 pF at the tip, R·C = 509 ns. If the bottom leg is the scope's ~9.1 kΩ, the bottom capacitance must be about 55 pF. That capacitance is not a component; it is the sum of
- the cable, which at low frequency behaves as a lumped capacitor (3M 1700-series twisted-pair flat cable: 52 pF/m signal-to-grounds, 44 pF/m within a pair; half a metre is roughly 22 to 26 pF),
- the plug PCB traces and edge connector,
- the scope's input capacitance behind the connector, which Siglent does not publish.
For OZ2CPU's values, 86.6 kΩ × 8.2 pF = 710 ns, asking for about 74 pF across the bottom leg. The differences between 5.6 pF and 8.2 pF designs are mostly differences in cable length and cable type.
What goes wrong when the rule is not met is subtle on a logic channel, because there is no trace on the screen to show overshoot or droop. Instead the error appears as timing:
- Under-compensated (C_top too small): the fast part of the edge is attenuated more than the DC ratio, and the signal creeps up to its final value over a few hundred nanoseconds. The comparator switches late, and later still at thresholds close to the logic high level. Narrow pulses shrink or disappear.
- Over-compensated (C_top too large): the edge overshoots and then sags. The comparator switches early, and a threshold placed near the top of the signal can produce a short glitch.
Both show up as a duty cycle that changes when you move the threshold. That gives a practical test: feed a clean square wave, measure its duty cycle with the scope's digital measurements, and sweep the threshold from 20 % to 80 % of the signal amplitude. A compensated probe gives the same duty cycle across the sweep.
Use C0G/NP0 capacitors. At 5.6 pF, the voltage and temperature coefficients of X7R would move the compensation around by tens of percent.
4. The cable is a transmission lineHalf a metre of cable is about 2.7 ns of delay (3M 1700 series: 5.35 ns/m, velocity factor 0.62). A logic edge from a modern CMOS part rises in 1 to 2 ns, shorter than the round trip down the cable and back. For those edges the cable is not a capacitor but a transmission line, and the design has to decide what happens to the reflections.
Pairing. In the author's probe every signal conductor in the 16-way 3M 1700/16 cable is twisted with its own ground conductor, eight pairs per pod. Each channel is then a balanced pair with a characteristic impedance of about 122 Ω, its own return path, and a small loop area. Crosstalk between channels drops sharply compared with a plain ribbon where eight signals share one or two grounds, and the return current of each edge flows right next to its signal.
The receiving end is effectively open. The scope end presents about 9 kΩ, a hundred times the cable impedance. An edge arriving there reflects with almost the full amplitude and travels back towards the tip.
The series resistors. Both the pod and the plug carry a 121 Ω resistor in series with each signal (120 Ω in OZ2CPU's design, 250 Ω and 370 Ω in mawyatt's sketch). They are not terminators in the usual sense, because neither end is a matched load, but they do two jobs:
- At the tip end, 121 Ω in series with the 5.6 pF compensation capacitor looks, at high frequency, like a source impedance close to the cable impedance. The reflection coming back from the open far end is absorbed there instead of bouncing back again. This is series (back) termination, the same technique used on fast PCB traces.
- At the scope end, 121 Ω isolates the line from the comparator's input capacitance and protection network, damping the ringing that a capacitive load at the end of a line produces.
The value is chosen to match the cable, which is why the author picked 121 Ω (E96) for a 122 Ω balanced pair, and why OZ2CPU notes that coax builds need around 75 Ω. The combined effect is a step at the comparator that settles within one round trip and crosses the threshold once.
Why not coax. The SPL2016 itself uses a multi-coax cable (about 45 Ω, 6.1 ns for 1.1 m). Coax gives the best isolation between channels but is expensive in 16-way form and stiff; twisted-pair flat cable is a very good compromise for the half-metre lengths a bench probe needs, and it is available off the reel.
(continued in the next post)
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