Author Topic: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes  (Read 53733 times)

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Online 2N3055

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #50 on: March 13, 2021, 10:37:48 pm »
here a lot of timebase settings, (this apply to all types of LA hardware, DIY and official hardware, it is a scope thing, confirmed)

the Digital got 2ns resolution (500MSa/s) so of course we expect the level change to be detected in 2ns steps...
however the clock to the digital sampler is NOT in phase or locked to the 2G samples the analog part uses !!!
so the jitter is random, and actually sometimes looking a bit funny depending on your curve frequency. (sample interference)

The same thing apply the other way : if you trigger on digital, they are now steady and locked to each other in fixed 2nS steps.
and now the analog curve gets "wide" from the random jitter. again it is 2nS wide, and it is only visible at speeds under 100nS/div.

the only way to fix this : is to lock the clocks together inside the scope design.

While you're at it, call Keysight and tell them to fix their scopes too.... :-DD

 

Offline oz2cpuTopic starter

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #51 on: March 13, 2021, 10:49:47 pm »
looks like the same 2nS digital resolution,
but see !! is the fixed :-) that is nice to see no random free running sub ps jitter
so this unit uses the same clock source,
how does it look, if you trigg on digital ? how is your analog looking ?
« Last Edit: March 14, 2021, 12:43:47 am by oz2cpu »
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Offline rf-loop

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #52 on: March 14, 2021, 10:41:20 am »
here a lot of timebase settings, (this apply to all types of LA hardware, DIY and official hardware, it is a scope thing, confirmed)

the Digital got 2ns resolution (500MSa/s) so of course we expect the level change to be detected in 2ns steps...
however the clock to the digital sampler is NOT in phase or locked to the 2G samples the analog part uses !!!
so the jitter is random, and actually sometimes looking a bit funny depending on your curve frequency. (sample interference)

The same thing apply the other way : if you trigger on digital, they are now steady and locked to each other in fixed 2nS steps.
and now the analog curve gets "wide" from the random jitter. again it is 2nS wide, and it is only visible at speeds under 100nS/div.

the only way to fix this : is to lock the clocks together inside the scope design.

Look like there is now some kind of misunderstanding about how oscilloscope works, how trigger works and how analog channel (yes only these) signal position is fine adjusted for minimal visible trigger jitter, as long as trigger is in analog channel. Btw, analog channels trigger engine is totally in digital side after ADC, fully and infinitely. But digital channels are just raw sampled after comparators, and just its 1/0 state is sampled.

And absolutely sure analog ADC and this digital channels sample use same clock. I do not believe, I know it. Period.

For  stop this bullshit spreading, please take pen and paper and analyze this and after 5 minutes you understand whu there exist random jitter. If you can not analyze it, then you need only believe when peoples who know, tell it. 3055 sure know it. Also I know.
Only problem is now your thinking and logical reasoning does not work properly. Where is this blind spot, you need solve it - or believe what others who know, say. 
Analog and digital side clock is same and samples synchronized.
Random jitter occurs and this is a natural and inevitable consequence of the operation of the system and is not even affected by the name of the manufacturer.

Btw, even with scope you can do some very simple demonstrations. Turn scope acquisition mode to slow. Turn display mode to Dots. After then use some different signals and also use single shots.
Do you find ANY single case when analog side and digital side do not stay hand in hand. No, there is not exceptions.

Also you need understand that analog side use fine positioning system based to fine interpolation between samples. But, digital side do not have this mechanism at all... because it can not do. Why, because there is not data for do it. Also this is true, independent of manufacturers. There is no manufacturer who can adjust something when there is no data for it. Only what can do for less jitter (based to this mechanism) is rise digital side sampling speed. It is very different when some may have 5GSa/s and one have 0.5Gsa/s. some manufactures have in some models same samplerate for digital and analog. Still there is is this jitter, and it is random. Inside one sample period edge can be where ever. If it is used for trig, then analog channel jitters relative to digital channel edge. Because true edge is randomly somewhere between these digital channel samples. But analog channel draw it, if there is more samples in this edge if you stop scope you can look where is true edge and then look how much digital side edge is in wrong place... think  carefully now why this digital edge is in wrong place... even when trigger was in digital channel. This is perhaps part of your blind point. With pen and paper you can easy see it. Think carefully what happen in analog side and digital side and how digital side trig.
Digital side do not trig to rising edge at all!!  Digital side trig to state! State may have changed in every position between previous and next sample. When sample state is changed, digital side generate trig. True state change can be just here or it can be just after previous sample. But same time analog side display where and how signal change (and if equal propagation delay with digital channel, same time). Now every turn it can be randomly where ever between these digital side samples. Random! Because external world is not locked to oscilloscope clock signal. (Random until you phaselock used test signal to oscilloscope sampling clock.)
If I have native english this is more easy to explain. But I have this FinChinglish.
« Last Edit: March 14, 2021, 10:43:03 am by rf-loop »
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Offline oz2cpuTopic starter

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #53 on: March 14, 2021, 11:23:09 am »
>stop this bullshit spreading

here where i come from, we try to talk nice, even if we dont agree

I would not call it BS, I just say : there is a free running clock on the digital 500MHz and another 2GHz on the analog,
since they are not locked in this unit, you get time jitter, when combining digital and analog and trig on one, and look at the other.
2nS is far from a real problem, all know that for sure.
but you need to go all the way down to 100ns/div for this not to bother your visual look and feel of your curves,
again : compleetly normal and there is a fundamental reason for this.
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Offline rf-loop

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #54 on: March 14, 2021, 11:55:02 am »
>stop this bullshit spreading

there is a free running clock on the digital 500MHz and another 2GHz on the analog,
since they are not locked in this unit, you get time jitter, when combining digital and analog and trig on one, and look at the other.


And still you continue this.

Where from you get this idea these clocks run wild.  ETA: I think this incorrect reasoning happen or can see here « Reply #45 on: Yesterday at 07:47:24 pm ».
Please think carefully why it is random. I have many times advice some small tools for correct this misunderstood.. paper and pen... run scope in dots mode... and run scope in slow acquisition mode so that every frame have only one acquisition. Watch these dots and watch these digital signal edges. Switch trig source between analog and digi ch. Use enough fast time scale (old term time base)  I hope some day blind spot get light.


 I can not understand what is base reason for this claim. ETA: (except if it is what can see in reply #45 what I just read more carefully)

Perhaps you can tell how much jitter is between these clock signals. Perhaps you can also tell where this jitter is added to this clock (this amount what we are now talking here). Source for both clocks is same. Amount of this jitter is and must be totally in different ballpark if think this 2ns sample interval time window and then external signal what can randomly be where ever inside this time window. This is main part of this jitter.
If you do not believe open it and measure these clocks.

Even when these clocks have some small jitter between each others (because in real world zero jitter is absolutely impossible than DC what do not exist in this universe) this is not reason for this random jitter we are talking now here.
« Last Edit: March 14, 2021, 12:21:21 pm by rf-loop »
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Offline oz2cpuTopic starter

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #55 on: March 14, 2021, 12:37:10 pm »
>Where from you get this idea these clocks run wild.  I can not understand what is base reason for this claim.

the sub ns sec jitter, the only way to explain it, (in my brain) is if the clocks are free running.
(and that case is the only thing we argue about :-)
I do agree i find it hard to belive they would design it like that,
it sounds smarter and cheaper to have only one clock source for the entire unit,
and again it is not a big practical problem, since most cases with digital and analog debugging at the same time,
you will ofcourse use a timebase at 100ns or slower
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Offline DL2XY

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #56 on: March 14, 2021, 12:40:24 pm »
Quote
there is a free running clock on the digital 500MHz and another 2GHz on the analog,
since they are not locked in this unit, you get time jitter, when combining digital and analog and trig on one, and look at the other.

Just for proof this is not the case here are some crosslinked screenshots from the Siglent SDS2000X Plus thread:





All are made with signals derived from scope clock (internal awg) so they are phase coherent to aquisition.
There is no more jitter than a fews picoseconds, regardless if triggered on analog or digital channels.
 
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Offline oz2cpuTopic starter

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #57 on: March 14, 2021, 01:05:27 pm »
you are a GENIUS DL2XY DANKE !!
perfect experiment to prove this : this means i was WRONG and i am not afraid to say so.
so the final words on jitter : all clocks are in fact locked and from the same source, digital, analog and awg,
I did the same experiment as you and all is now super,
there is still jitter, but it is ALOT less, and it is fixed like shown here,

by the way, I dont understand how you made the first picture ?
you are clocking an 8 bit ripple counter ?
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Offline DL2XY

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #58 on: March 14, 2021, 01:12:09 pm »
Thank you.

You can even use this method in practise, just clock your target system from internal awg (i did so for the walking bit pattern).
If i need higher clock rates than 10 Mhz i use the internal awg to synchronize my SDG6052, so i can create coherent signals up to 500Mhz.

73 Walter
 
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Online 2N3055

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #59 on: March 14, 2021, 01:43:59 pm »
>stop this bullshit spreading

here where i come from, we try to talk nice, even if we dont agree

I would not call it BS, I just say : there is a free running clock on the digital 500MHz and another 2GHz on the analog,
since they are not locked in this unit, you get time jitter, when combining digital and analog and trig on one, and look at the other.
2nS is far from a real problem, all know that for sure.
but you need to go all the way down to 100ns/div for this not to bother your visual look and feel of your curves,
again : compleetly normal and there is a fundamental reason for this.

I agree, politeness is nice, but  you really should stop insisting repeating statements that are simply wrong, after being repeatedly told they are wrong.
There are no different clocks for digital and analog sampling inside scope. Period. And it is not an opinion. I know that.

What you see is artefact of analog channel correction for trigger point, difference in sampling clock for digital and analog, and sampling (timing errors) for discrete logic sampling between two asynchronous timing domains.

Keysight has same problem, but they are deciding to round up display to discrete steps, while Siglent shows you exactly how it would look if you were to lock analog CRT scope to a logic analyser.
In the end they both show same uncertainties. MSO from Picoscope goes even further, they don't even draw vertical edges, but a block that is as wide as uncertainty is.

Here is another screen from Keysight. Here we are triggering from D0.
You will see that analog signal indeed jitters around, and also that the very trigger point of sampled signal also jitters around. How can THAT be, if we are triggering on that very edge.

Explanation lies in how Keysight implements the engine. 

So what is better.  Keysight way where they are rounding timing information to show "pretty" display, or Siglent that shows you jitter between synchronous and asynchronous sampling (in regards to outside measured signal) ? They both show same uncertainty period, and if you see any artefacts on edges, you are trying to measure something too fast. So what is better?

Here is my opinion: They will both do the job of looking at the slow serial busses in the end.
But I prefer Siglent way, because it is exact representation of physical sampling processes as they are happening. It, in fact shows on the screen exact correlation of two clock domains and how the signal was sampled by scope digital channels correlated to input signal (represented by analog channel which is made synchronized to input by software algorithm)

PS: before posting this I realized DL2XY made great post proving this all by synchronizing input signal via using internal AWG.
 
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Online 2N3055

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #60 on: March 14, 2021, 01:49:44 pm »
I threw together diagram that shows sampling:



Analog channels are sampled with clock that is synchronous to internal scope clock, but then interpolator adjusts them left and right to place them correctly at trigger time zero. That makes it synchronized to external signal on input. Digital channels stay at physical sample points, because they have no way to measure phase difference to input signal and make timing corrections.
So analog and digital signals will not be synchronous, and difference will be defined by correlation of frequency and phase off the both clock domains (external signal/scope clock).
It's magnitude will be defined by sampling clock and difference in sampling clock for analog and digital channels.
« Last Edit: March 14, 2021, 01:58:16 pm by 2N3055 »
 
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Offline oz2cpuTopic starter

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #61 on: March 14, 2021, 02:16:03 pm »
thanks a lot 3055 for the nice drawing, I had the idea my post #57
could be the final of this one ?

maybe we could make an even better drawing ?
2 Ghz scope clock for analog
500 Mhz scope clock for digital
those two , we now know are locked together,
so this means anything we see on analog or digital channels, must happen in a clock transition,
now to the magic that confused at least only me :
my case was the incoming analog/digital signal was free running,
I had the idea BOTH analog and digitals where sampled at the SAME (but of course using their own speed 500/2G)
if I come with only one single pulse, its timing will differ on digital, versus analog,
not in fixed 2ns hops, but in anything random, under 2ns, from measurement.
that is, a bit funny if you think about it :-)
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Online 2N3055

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #62 on: March 14, 2021, 02:42:22 pm »
thanks a lot 3055 for the nice drawing, I had the idea my post #57
could be the final of this one ?

maybe we could make an even better drawing ?
2 Ghz scope clock for analog
500 Mhz scope clock for digital
those two , we now know are locked together,
so this means anything we see on analog or digital channels, must happen in a clock transition,
now to the magic that confused at least only me :
my case was the incoming analog/digital signal was free running,
I had the idea BOTH analog and digitals where sampled at the SAME (but of course using their own speed 500/2G)
if I come with only one single pulse, its timing will differ on digital, versus analog,
not in fixed 2ns hops, but in anything random, under 2ns, from measurement.
that is, a bit funny if you think about it :-)

Well for the detailed drawing, that's a homework for you, I did mine..  ^-^
But detailed diagram is not important. Scope can be put at timebase where both will be 500 MSps/sec and my diagram shows that particular condition, and also it makes it clearer.

As for the question, that is what I try to explain: both A/D converters (on analog CH) and latches after comparators (for digital CH) are sampled synchronously.

But trigger point on analog signal will be anywhere in between two samples. Look at my diagram.
Then in postprocessing, scope will declare that point 0 time (because scope is considering input signal the master, which it should).
Since digital channels are still aligned to scope clock, there will be skew between scope trigger point (zero time) and those edges.
And on every trigger that skew will be different.

So scope is actually trying hard to show you exactly where input signal was in correlation to scope digital sampling clock. It is not jitter, it is actual true representation at which point in time was every edge sampled. It is a diagram of correlation of outside signal periodicity and periodicity on internal sampling clock.

A small reading recomendation:

http://hparchive.com/Journals/HPJ-1997-04.pdf


Back in the olden days, we used synchronous logic analyzers, that were clocked from DUT, to solve this problem.
For this type of asynchronous sampling LA (like all MSO scopes today are) you get edge timing limits that need to be taken into consideration. For protocol analysis, 10X oversampling will work quite well, which means that you should be able to decode quite fast serial protocols with 500 MPs/s.
For accurate timing analysis, you should use analog channels. In which case you can get very good results, and resolve less than 100 of picosecond timing.
Not bad for a inexpensive scope...

 
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Offline oz2cpuTopic starter

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #63 on: March 14, 2021, 03:32:35 pm »
EXACTLY !
and for the record, I did update my "complain" video, and i also updated the bug report post.
thanks again for helping with the deep diggin, now I need to order a new signal generator,
since this scope reveal other unwanted artifacts from my old, I am looking at SDG6022X
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Offline rf-loop

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #64 on: March 15, 2021, 05:06:13 am »

Keysight has same problem, but they are deciding to round up display to discrete steps, while Siglent shows you exactly how it would look if you were to lock analog CRT scope to a logic analyser.
In the end they both show same uncertainties. MSO from Picoscope goes even further, they don't even draw vertical edges, but a block that is as wide as uncertainty is.

Here is another screen from Keysight. Here we are triggering from D0.
You will see that analog signal indeed jitters around, and also that the very trigger point of sampled signal also jitters around. How can THAT be, if we are triggering on that very edge.


It is weird. Really weird.

Then a small side jump next to the thing
MegaZoom IV give many advantages over many other scopes but...

This article (Keysight blog)
https://keysightoscilloscopes.wordpress.com/category/oscilloscope-triggering/

is somehow fun to read... and when look publisher and authors... there is also some drawings.. and note that this time "all" was Megazoom IV. 

This not reason and partially nonsense but... trigger in analog side is also ancient analog sidepathway / comparator based system. Due to megazoom IV advantages they need advertise these advantages and hype these and then keep mouth closed about other things as example that it have conventional analog side pathway trigger system - if I have understood right.
I have not seen any sales brochure where is imagined Megazoom IV where is also displayed where from trigger "bloc"get signal... in every image this line is missing.
Of course well done analog side pathway trigger system can be good/very good (and in top - expensive. Perhaps LeCroy know how expensive)...
Analog trigger can also see things what full digital side trigger can not see at all, both systems have some but different disadvantages. Simplest example, levels what are over ADC FS, analog trigger can still work. Also, analog side pathway trigger is never ever fooled by alias! But, other hand it may get different signal shape and phase. Digital side digital trigger engine do not know if ADC output is ADC produced alias (down conversion) or real.

By Colin F. Mattsonin Oscilloscope Triggering, OscilloscopesJuly 27, 2016: "How It Works

Most real-time oscilloscopes have an “analog” trigger system.  This system is actually a mishmash of analog circuitry and digital counters but it relies on input from analog comparators fed from the scope pre-amp.  Some oscilloscopes now feature a “digital” trigger, meaning that the trigger system is entirely digital and is fed with integer data from the ADC output.  Both types of systems perform the same function; evaluating whether or not all of the configured trigger conditions are met at a given moment in time.  Because fully digital trigger systems are fairly rare, we’ll focus on analog trigger systems."

Is it possible they fine adjust analog signal even when trigger is from digital channel. If they do this... perhaps there is more artists than engineers... for "nice looking images". Without further tests this can not know.
Maybe it’s not even very interesting. If truth do not look all nice do not still hide it or bend it looking more nice, as long as we talk test and measurements instruments!

« Last Edit: March 15, 2021, 05:13:47 am by rf-loop »
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Offline mawyatt

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #65 on: March 15, 2021, 04:13:47 pm »
The old analog Tektronix scopes had the best trigger system of any available scope at the time, much better than HP. Like much of the old Tektronix analog scopes, this trigger system was a masterpiece of engineering (like transistor ft doubler preamp for example) and utilized ECL gates as fast analog differential limiting amplifiers in the trigger system because of the ECL transistor speed. I doubt much improvement over this superb analog based trigger system over the years other than use of higher ft transistors for faster triggering.

Does any scope have both digital and analog triggering capability?

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Offline oz2cpuTopic starter

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #66 on: March 15, 2021, 04:27:43 pm »
the last two posts super interesting, but now we are doing it again.. change topic in a thread :-)
how about we find out how the trigger is really made in the Siglent SDS2000 scope ? and continue in the Siglent scope thread ?
since this scope got FPGA front end to handle the ADC's I would guess it is all done in fpga "hardware"
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Offline tautech

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #67 on: March 15, 2021, 07:57:11 pm »
the last two posts super interesting, but now we are doing it again.. change topic in a thread :-)
how about we find out how the trigger is really made in the Siglent SDS2000 scope ? and continue in the Siglent scope thread ?
since this scope got FPGA front end to handle the ADC's I would guess it is all done in fpga "hardware"
Trigger discussion is highly relevant to this thread and it's already been disclosed the LA trigger path is different to the analog input digital trigger path where instead the LA path uses comparators.

As has already been pointed out the comparator only needs see its threshold has been met not at what level so combined with the slower LA sampling rate that introduces the timing uncertainties we see as jitter.
It's not like this is a big deal when investigating analog to digital signal conversion when using a LA trigger when we have a deep memory scope as we can record the analog events leading up to the digital trigger.
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Offline DL2XY

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #68 on: March 15, 2021, 10:05:52 pm »
There is another point to take into account doing timing analyses:
The trigger level is not absolute, each comparator has a hysteresis of about 650mV (relative to input of 10:1 divider).
Depending on rise and fall times that leads to additional delays.



« Last Edit: March 15, 2021, 10:10:09 pm by DL2XY »
 

Offline rf-loop

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #69 on: March 16, 2021, 04:28:34 am »
There is another point to take into account doing timing analyses:
The trigger level is not absolute, each comparator has a hysteresis of about 650mV (relative to input of 10:1 divider).
Depending on rise and fall times that leads to additional delays.

Handling hysteresis is different in analog channels and digital channels. In analog channel hysteresis window (wide or narrow hysteresis, depending settings) is always "before" defined trigger level. If user change rising edge trig to falling edge, trig level point is same but hysteresis is moved from downside to upside.
 
But as far as I know example usual PECL comparators have just HW fixed Vhysteresis (usually Vhys is settable example using external resistor). Ordinarily threshold level "0" is center of hysteresis window, so +Vhys/2 is above the threshold level and -Vhys/2 is below the threshold level.
This is very different in analog channel trigger. In rising direction of trig, example edge trig, Vhys is below the threshold and for falling direction of trig Vhys is above the threshold level. In analog side also amount of Vhys is proportional, and even more, we have there two user settable proportional amount of hysteresis. (amount of Vhys is proportional mean that it is some amount from used V/div. I do not remember SDS2000X+ but some scope may have example narrow hys 0.3div and wide hys 0.8div (SDS1000X-E series) explained here but unfortunately by Finnish language what is my native lang. https://siglent.fi/oskilloskooppi-digital-trigger-system-siglent.html )

So, example, rising edge, if we set analog channel trig level to 1.5V and digital channels threshold level to 1.5V  trig position in time axis is different. 
Before edge analog is below [Trig level - Vhys].  And Digital side signal is below [Vthreshold - Vhys/2].
Now when signal  start rise in analog side first it cross over [Triglevel - Vhys] and after then it reach [Trig level], result is "Trig"

If trigger is in Digital side. Signal start rise and first it cross over [Threshold level - Vhys/2]  after then come [threshold level] but nothing happen... after then it cross over [threshold level + Vhys/2] and then result is "Trig". 
Time difference depend this rising time ( pitch angle).

So, yes there is difference and user need understand it if he is working with slow digital side rising times and are looking things in nanoseconds range.  Btw, how much it is if rising slope is slow 10ns.  ;) 

User need just understand this for avoid some traps, as is always important what ever feature is used. "Know your tools..." and so on.



About DIY  LA probe. What is thickness  of gold (and what alloy)  in contacts because this is for frequent plug in - plug out use.
Also, PCB material is important. If it is glass fiber etc.. its edge, even if it have some angle, may cause grinding in connector contacts surface. Perhaps example teflon do not so easy wear and tear this connector. Also contact surface gold or other metal alloys are different for resist wear and tear + corrosion + thermal EMF (what is not important just in this case). But it need resist wear and tear and corrosion/oxidation.  Example PCI-E connectors are not at all designed for continuous and frequent plug in plug out. It can last but need use carefully and cable connector need take care about avoid this PCI-E connector wearing.


Cable. (I do not have any idea about prices, but technically interesting)

There is also available many small dimension coaxial cables manufactured example for medical use. No need be just flat ribbon coaxial.. just example multiple coaxial in soft very flexible (also in low temperatures) silicon etc tube..

Example Coonerwire  http://www.coonerwire.com/mini-coax/  CW2040-3695 F  what is 95ohm coaxial with 0.062 O.D. and 13.5pF capacitance. Or CW2040-3650 F what is 50 ohm, 29.5pF  O.D  1mm aka 0.039"

And whole catalog top quality cables  http://www.coonerwire.com/cooner_catalog_rev9-8.pdf

Some wires are perhaps bit expensive, example pure gold cables
« Last Edit: March 16, 2021, 04:55:56 am by rf-loop »
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Offline oz2cpuTopic starter

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #70 on: March 16, 2021, 08:04:45 am »
>User need just understand this for avoid some traps, as is always important what ever feature is used. "Know your tools..." and so on.

EXACTLY and that is why it is very smart we deep dive into all this,
using the LA alone, versus together with digital, what happens, and most important why,
this way we all get a smarter, faster, and more happy day,
next time we need to debug some real life stuff :-)
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EMC RF SMPS SI PCB LAYOUT and all that stuff.
 

Offline rf-loop

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #71 on: March 16, 2021, 10:12:50 am »
>User need just understand this for avoid some traps, as is always important what ever feature is used. "Know your tools..." and so on.

EXACTLY and that is why it is very smart we deep dive into all this,
using the LA alone, versus together with digital, what happens, and most important why,
this way we all get a smarter, faster, and more happy day,
next time we need to debug some real life stuff :-)

Y E S
I drive a LEC (low el. consumption) BEV car. Smoke exhaust pipes - go to museum. In Finland quite all electric power is made using nuclear, wind, solar and water.

Wises must compel the mad barbarians to stop their crimes against humanity. Where have the wises gone?
 

Offline mawyatt

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #72 on: March 16, 2021, 02:47:01 pm »
Here's the latest concept we're looking into. This features an expansion of the base connector case to the MSO to allow dual 16 pin 2 row headers, one for digital inputs 0-7 and the other for 8-15. These are designed to support 8 pairs of twisted ribbon cable, or a common 16 wire ribbon cable with GSGS type configuration.

With this configuration the base case can remain attached to the MSO and the ribbon cables plugged into the base header connectors, also allows different cable types or lengths to be used between the Base and the Probe POD. The POD supports a 16 pin header with 8 digital lines, and 8 ground lines, but also can directly support single lines with a 1 pin header (Dupont type).

Should be a very flexible architecture allowing experimenting with different cable types & lengths. We've just ordered, per recommendation by oz2cpu, a 3D printer and downloaded Fusion 360 to try and "get up to speed" with 3D modeling and printing, not sure how long this will take before any actual 3D printed cases emerge since absolutely no prior experience with any of this 3D stuff. Also, ordered a few twisted pair ribbon cable types to evaluate and measure characteristics, along with various header types, connector pins & crimping tools.

Custom PCBs for the Base and PODs are not a problem or big delay, and will be flexible enough to allow variations and maintain good signal integrity.

Anyway, putting this out for others to comment and maybe even consider.
« Last Edit: March 16, 2021, 02:55:38 pm by mawyatt »
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Offline xandmann

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #73 on: March 17, 2021, 08:52:32 am »
According to a test report regarding PCIE connectors from Samtec, the connector in question will withstand (depending on the angle of pull) between 300-600 mating cycles and a 90 deg pull force of 50 kg.
So using "bare PCB" adapter solutions without 3D printed casing shouldn't be a problem, however depending on ones bench setup frequent insertion/removal might cause problems in the long run.
« Last Edit: March 17, 2021, 08:54:23 am by xandmann »
 

Offline oz2cpuTopic starter

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Re: DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
« Reply #74 on: March 17, 2021, 09:34:00 am »
i prefer, and suggest, and recommend to use some sort of steering of the pcb into the scope LA socket,
this way it goes in correctly, stay in right angles, and this way the scope part will live longest possible,
the work is worth it, if anyone like fusion files, or step files, or stl files for free, simple PM me.
AND you are also welcome to get gerber files or altium design files
Radioamateur OZ2CPU, Senior EE at Prevas
EMC RF SMPS SI PCB LAYOUT and all that stuff.
 


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