Products > Test Equipment
DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes
oz2cpu:
>Where from you get this idea these clocks run wild. I can not understand what is base reason for this claim.
the sub ns sec jitter, the only way to explain it, (in my brain) is if the clocks are free running.
(and that case is the only thing we argue about :-)
I do agree i find it hard to belive they would design it like that,
it sounds smarter and cheaper to have only one clock source for the entire unit,
and again it is not a big practical problem, since most cases with digital and analog debugging at the same time,
you will ofcourse use a timebase at 100ns or slower
DL2XY:
--- Quote ---there is a free running clock on the digital 500MHz and another 2GHz on the analog,
since they are not locked in this unit, you get time jitter, when combining digital and analog and trig on one, and look at the other.
--- End quote ---
Just for proof this is not the case here are some crosslinked screenshots from the Siglent SDS2000X Plus thread:
All are made with signals derived from scope clock (internal awg) so they are phase coherent to aquisition.
There is no more jitter than a fews picoseconds, regardless if triggered on analog or digital channels.
oz2cpu:
you are a GENIUS DL2XY DANKE !!
perfect experiment to prove this : this means i was WRONG and i am not afraid to say so.
so the final words on jitter : all clocks are in fact locked and from the same source, digital, analog and awg,
I did the same experiment as you and all is now super,
there is still jitter, but it is ALOT less, and it is fixed like shown here,
by the way, I dont understand how you made the first picture ?
you are clocking an 8 bit ripple counter ?
DL2XY:
Thank you.
You can even use this method in practise, just clock your target system from internal awg (i did so for the walking bit pattern).
If i need higher clock rates than 10 Mhz i use the internal awg to synchronize my SDG6052, so i can create coherent signals up to 500Mhz.
73 Walter
2N3055:
--- Quote from: oz2cpu on March 14, 2021, 11:23:09 am --->stop this bullshit spreading
here where i come from, we try to talk nice, even if we dont agree
I would not call it BS, I just say : there is a free running clock on the digital 500MHz and another 2GHz on the analog,
since they are not locked in this unit, you get time jitter, when combining digital and analog and trig on one, and look at the other.
2nS is far from a real problem, all know that for sure.
but you need to go all the way down to 100ns/div for this not to bother your visual look and feel of your curves,
again : compleetly normal and there is a fundamental reason for this.
--- End quote ---
I agree, politeness is nice, but you really should stop insisting repeating statements that are simply wrong, after being repeatedly told they are wrong.
There are no different clocks for digital and analog sampling inside scope. Period. And it is not an opinion. I know that.
What you see is artefact of analog channel correction for trigger point, difference in sampling clock for digital and analog, and sampling (timing errors) for discrete logic sampling between two asynchronous timing domains.
Keysight has same problem, but they are deciding to round up display to discrete steps, while Siglent shows you exactly how it would look if you were to lock analog CRT scope to a logic analyser.
In the end they both show same uncertainties. MSO from Picoscope goes even further, they don't even draw vertical edges, but a block that is as wide as uncertainty is.
Here is another screen from Keysight. Here we are triggering from D0.
You will see that analog signal indeed jitters around, and also that the very trigger point of sampled signal also jitters around. How can THAT be, if we are triggering on that very edge.
Explanation lies in how Keysight implements the engine.
So what is better. Keysight way where they are rounding timing information to show "pretty" display, or Siglent that shows you jitter between synchronous and asynchronous sampling (in regards to outside measured signal) ? They both show same uncertainty period, and if you see any artefacts on edges, you are trying to measure something too fast. So what is better?
Here is my opinion: They will both do the job of looking at the slow serial busses in the end.
But I prefer Siglent way, because it is exact representation of physical sampling processes as they are happening. It, in fact shows on the screen exact correlation of two clock domains and how the signal was sampled by scope digital channels correlated to input signal (represented by analog channel which is made synchronized to input by software algorithm)
PS: before posting this I realized DL2XY made great post proving this all by synchronizing input signal via using internal AWG.
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