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DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes

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2N3055:
I threw together diagram that shows sampling:



Analog channels are sampled with clock that is synchronous to internal scope clock, but then interpolator adjusts them left and right to place them correctly at trigger time zero. That makes it synchronized to external signal on input. Digital channels stay at physical sample points, because they have no way to measure phase difference to input signal and make timing corrections.
So analog and digital signals will not be synchronous, and difference will be defined by correlation of frequency and phase off the both clock domains (external signal/scope clock).
It's magnitude will be defined by sampling clock and difference in sampling clock for analog and digital channels.

oz2cpu:
thanks a lot 3055 for the nice drawing, I had the idea my post #57
could be the final of this one ?

maybe we could make an even better drawing ?
2 Ghz scope clock for analog
500 Mhz scope clock for digital
those two , we now know are locked together,
so this means anything we see on analog or digital channels, must happen in a clock transition,
now to the magic that confused at least only me :
my case was the incoming analog/digital signal was free running,
I had the idea BOTH analog and digitals where sampled at the SAME (but of course using their own speed 500/2G)
if I come with only one single pulse, its timing will differ on digital, versus analog,
not in fixed 2ns hops, but in anything random, under 2ns, from measurement.
that is, a bit funny if you think about it :-)

2N3055:

--- Quote from: oz2cpu on March 14, 2021, 02:16:03 pm ---thanks a lot 3055 for the nice drawing, I had the idea my post #57
could be the final of this one ?

maybe we could make an even better drawing ?
2 Ghz scope clock for analog
500 Mhz scope clock for digital
those two , we now know are locked together,
so this means anything we see on analog or digital channels, must happen in a clock transition,
now to the magic that confused at least only me :
my case was the incoming analog/digital signal was free running,
I had the idea BOTH analog and digitals where sampled at the SAME (but of course using their own speed 500/2G)
if I come with only one single pulse, its timing will differ on digital, versus analog,
not in fixed 2ns hops, but in anything random, under 2ns, from measurement.
that is, a bit funny if you think about it :-)

--- End quote ---

Well for the detailed drawing, that's a homework for you, I did mine..  ^-^
But detailed diagram is not important. Scope can be put at timebase where both will be 500 MSps/sec and my diagram shows that particular condition, and also it makes it clearer.

As for the question, that is what I try to explain: both A/D converters (on analog CH) and latches after comparators (for digital CH) are sampled synchronously.

But trigger point on analog signal will be anywhere in between two samples. Look at my diagram.
Then in postprocessing, scope will declare that point 0 time (because scope is considering input signal the master, which it should).
Since digital channels are still aligned to scope clock, there will be skew between scope trigger point (zero time) and those edges.
And on every trigger that skew will be different.

So scope is actually trying hard to show you exactly where input signal was in correlation to scope digital sampling clock. It is not jitter, it is actual true representation at which point in time was every edge sampled. It is a diagram of correlation of outside signal periodicity and periodicity on internal sampling clock.

A small reading recomendation:

http://hparchive.com/Journals/HPJ-1997-04.pdf


Back in the olden days, we used synchronous logic analyzers, that were clocked from DUT, to solve this problem.
For this type of asynchronous sampling LA (like all MSO scopes today are) you get edge timing limits that need to be taken into consideration. For protocol analysis, 10X oversampling will work quite well, which means that you should be able to decode quite fast serial protocols with 500 MPs/s.
For accurate timing analysis, you should use analog channels. In which case you can get very good results, and resolve less than 100 of picosecond timing.
Not bad for a inexpensive scope...

oz2cpu:
EXACTLY !
and for the record, I did update my "complain" video, and i also updated the bug report post.
thanks again for helping with the deep diggin, now I need to order a new signal generator,
since this scope reveal other unwanted artifacts from my old, I am looking at SDG6022X

rf-loop:

--- Quote from: 2N3055 on March 14, 2021, 01:43:59 pm ---
Keysight has same problem, but they are deciding to round up display to discrete steps, while Siglent shows you exactly how it would look if you were to lock analog CRT scope to a logic analyser.
In the end they both show same uncertainties. MSO from Picoscope goes even further, they don't even draw vertical edges, but a block that is as wide as uncertainty is.

Here is another screen from Keysight. Here we are triggering from D0.
You will see that analog signal indeed jitters around, and also that the very trigger point of sampled signal also jitters around. How can THAT be, if we are triggering on that very edge.


--- End quote ---

It is weird. Really weird.

Then a small side jump next to the thing
MegaZoom IV give many advantages over many other scopes but...

This article (Keysight blog)
https://keysightoscilloscopes.wordpress.com/category/oscilloscope-triggering/

is somehow fun to read... and when look publisher and authors... there is also some drawings.. and note that this time "all" was Megazoom IV. 

This not reason and partially nonsense but... trigger in analog side is also ancient analog sidepathway / comparator based system. Due to megazoom IV advantages they need advertise these advantages and hype these and then keep mouth closed about other things as example that it have conventional analog side pathway trigger system - if I have understood right.
I have not seen any sales brochure where is imagined Megazoom IV where is also displayed where from trigger "bloc"get signal... in every image this line is missing.
Of course well done analog side pathway trigger system can be good/very good (and in top - expensive. Perhaps LeCroy know how expensive)...
Analog trigger can also see things what full digital side trigger can not see at all, both systems have some but different disadvantages. Simplest example, levels what are over ADC FS, analog trigger can still work. Also, analog side pathway trigger is never ever fooled by alias! But, other hand it may get different signal shape and phase. Digital side digital trigger engine do not know if ADC output is ADC produced alias (down conversion) or real.

By Colin F. Mattsonin Oscilloscope Triggering, OscilloscopesJuly 27, 2016: "How It Works

Most real-time oscilloscopes have an “analog” trigger system.  This system is actually a mishmash of analog circuitry and digital counters but it relies on input from analog comparators fed from the scope pre-amp.  Some oscilloscopes now feature a “digital” trigger, meaning that the trigger system is entirely digital and is fed with integer data from the ADC output.  Both types of systems perform the same function; evaluating whether or not all of the configured trigger conditions are met at a given moment in time.  Because fully digital trigger systems are fairly rare, we’ll focus on analog trigger systems."

Is it possible they fine adjust analog signal even when trigger is from digital channel. If they do this... perhaps there is more artists than engineers... for "nice looking images". Without further tests this can not know.
Maybe it’s not even very interesting. If truth do not look all nice do not still hide it or bend it looking more nice, as long as we talk test and measurements instruments!

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