DIY Logic Analyzer Probe and Pods for Siglent (and LeCroy) scopes

[oz2cpu]

Here we go, the isolated thread for this project.
More will come shortly.
Thanks to TK and Mike and tautech, for technical help and collaboration.
Any body else are also welcome to come with ideas or comments.
----
The motivation for DIY : original set is at least 400 Euro, and the hardware dont contain anything fancy or expensive.
Some scopes might need a software upgrade or license code to access the logic analyzer features.
I have been playing with a logic analyzer plug in pcb for Siglet scopes.
(NOTE: This type of LA connector will also mate and work with a lot other scope brands too, see bottom of this post)
see the attached pictures, it is 4 layers,
i am also making a 3D printable design to make it click in and hold in,
hold and secure the cables, this way it is super easy to make your own logic analyzer cables,
any type, and any length you like.

I also plan to make a double BNC holder for this pcb,
so the 3D print hold the two extra BNC inputs, so they are nice and stable for two extra 1:1 probes

if any one is interested, PM me.

Scopes this will fit: (please tell me more if you know for sure)
Siglent SDS2000X / SDS2000X Plus / SDS5000X / SDS6000 Series (Siglent SPL2016 Logic Probes)
Teledyne LeCroy T3DSO2000/2000A Series Oscilloscopes (T3DSO2000-LS Logic Probes)
Tektronix MDO3000 series (not confirmed)

Free Gift: 3D printable dust cover for LA connector hole : https://www.thingiverse.com/thing:4779225

LATEST NEWS : MY STOCK IS EMPTY.
I DO NOT PLAN TO MAKE AND SELL MORE.
ALTIUM AND GERBER FILES ARE NOW IN THE ZIP FILES HERE:

my 3D design files : https://www.thingiverse.com/thing:4784443

TheDefpom 3D modified files :  https://www.thingiverse.com/thing:4964027  see reply 151

[oz2cpu]

the pcb is on its way
so mean while i work with 3D design of the casing
the lock parts are very small, and hard to 3D print,
I am working with several ideas for this, one is even to drop the locking, since you dont really pull the wires
and the connector got a good hold of the pcb anyways.

[oz2cpu]

this is the probe tip from HP
the good TK found this info.

I want to split the 250 ohm into two resistors, like this:
i expect the two 120 ohm needs to match the cable used,
and also trim the value of the 8.2pF for hi speed performance,

see attached

[oz2cpu]

The PCB edge connector needs to be sanded to a well defined angle
I searched the net carefully, and found a bit different results,
from 20 to 40 deg.
so here is my idea : a sanding holder in 3D printed plastic, so the edge can be made nice and straight at correct angle,
we want to take good care about the scope connector, so i think 20 deg is better

[tautech]

SPL2016 16ch LA probe fits the following Siglent DSO ranges:
SDS2000X
SDS2000X Plus
SDS2000X HD
SDS5000X
SDS6000A

[oz2cpu]

POD design idea,
now step and stl files are in the Thingiverse link

[tautech]

What's the preference for the LA cables ?

2x flat 8 shielded cores to mimic the OEM ?
Or 2 flat 10 way cables with an over shield ?
Impedance ?

Not easy to find this stuff especially a nice flexible rubberised one like OEM use.
Belden 9L283XX is getting there 0.6" wide x 0.12 thick
https://www.interstatewire.com/files/9L28310.pdf

[oz2cpu]

my pref would be 2 x 8 flat twisted type, in a kind of thinner type over the normal ribbon type,
if only I could find that easy

[oz2cpu]

>BTW what connector does the Siglent use? Or better yet what did you use for the edge connector for your PCB layout?

I use 2 x 8 solder pads
spaced 2.54mm
this means we can use male or female standard pins to match what ever type of hook system we can find

siglent pods are with 2 x 10 female
as shown here, dont know the pin out of their pods

[mawyatt]

tautech,

I think the intent here is to not try and duplicate the Siglent performance but the function. The cables Siglent uses are expensive high quality multi-coaxial types I believe, the one you mentioned I was only able to find a minimum 100' at a cost of $400~500 + shipping. Also the Siglent has a nice Base and Pod units, as well as the nice flexable probe leads. So the Siglent is 1st Class High End Professional grade, like most of their equipment. However I do think it's expensive for most. The cost for the Logic Analyzer for the lower end scopes seems more justified with the active interface electronics and such in the base and pods, Siglent elected to move these active interface electronics inside the higher end scopes so the Logic Analyzer becomes totally passive. Anyway this might open up the possibility for a low cost alternative LA, maybe even DIY, for use with the Siglent higher end scopes.

Here's some additional supporting sketches for what I think oz2cpu is intending, a low cost DIY replacement for the Siglent Logic Analyzer that performs well. I've been looking into a 3M twisted pair cable to replace the flat coaxial cable in the Siglent, this is #28 AWG twisted wire with an impedance of ~130 ohms. Believe this can be adapted to work with the Siglent scopes at acceptable levels for most needs. The proper cable termination and such will need to be developed and likely aided with some simulations and testing, as few of us are prepared to get involved to hopefully make this happen.

Any ideas or support is welcome.

Best,

[mawyatt]

More Sketches.

Best,

[oz2cpu]

are they any good ?

https://www.ebay.com/itm/Goupchn-Mini-Grabber-SMD-IC-Test-Hook-Clip-Jumper-Probe-for-Logical-Analyzer/133521515268

[oz2cpu]

or how about this, really cheap

https://www.ebay.com/itm/Logic-Analyzer-Dupont-Female-Cable-Probe-Test-Hook-Clip-For-Arduino-Raspberry-Pi/123043795875

[tautech]

are they any good ?

https://www.ebay.com/itm/Goupchn-Mini-Grabber-SMD-IC-Test-Hook-Clip-Jumper-Probe-for-Logical-Analyzer/133521515268

Yep they look fine and pretty similar to OEM.
IMO 2 lots of 12pcs of 6 colors @ USD13.99 are the ones to go for.

or how about this, really cheap

https://www.ebay.com/itm/Logic-Analyzer-Dupont-Female-Cable-Probe-Test-Hook-Clip-For-Arduino-Raspberry-Pi/123043795875

Garbage, don't touch them.
Tiny wiggle or bit of stress and they come disconnected.

[oz2cpu]

thanks a lot mate, that saved me a lot of trouble :-)

could have been cool if only they existed in correct color codes from 0 to 9
so i have to find a way to add a label, and if they are colored at the same time, i end up being confused
since i cant turn off my brains color decoder

[tautech]

thanks a lot mate, that saved me a lot of trouble :-)

could have been cool if only they existed in correct color codes from 0 to 9
so i have to find a way to add a label, and if they are colored at the same time, i end up being confused
since i cant turn off my brains color decoder

It depends some on how you break out from the PCi-e connector.
If into two 8 channel leads as OEM do you might just be using 8 LA leads so only one ribbon is used to where you have the breakout again into the fly-leads and grabbers. OEM have tiny colored split beads on each fly-lead as well as matching colors for each channel on the fly-lead breakout fitting that I mentioned in another recent post is a 20 pin connector with 10 pins unused. 2 Gnds and 8 LA channels.

A few pics of SPL2016 from my archives.
Last added confirms the LA probe mates with a PCI-e socket form a PC mainboard.

[mawyatt]

Like shown in the hand sketches above, here's a couple early efforts at a base PCB that plugs into the scope interface and has two 8 twisted pair cable inputs (bits 0-7 & 8-15). Each 8 twisted pair cable interfaces to the separate POD PCB which has a 10 pin Connector to support 8 data bit probe leads and 2 ground leads.

Quickly done and needs verifying the scope connector leads are correct.

Best,

[oz2cpu]

you need to cut/mill the pcb as shown here in red,
and when you do, you loose connection to some of the GND pads,
also you got tracks in and out of other channels, it is high impedance stuff with fast rise times,
so i would be worried a bit about cross talk,
that is why i use a 4 layer pcb, and located all channels at most possible channel to channel distance.

[mawyatt]

Yeah didn't know what the proper connector interface dimensions are, so was just quickly done as shown without any regard for this. Do you know the interior scope connector, or have a data sheet which shows the proper dimensions for the PCB connector? Also, what scope digital input connector pins on A and B are used for the digital bit lines 0-7 and 8-15? Used your PCB layout as a guide, but could have things flipped.

The grounds shouldn't be a problem because the ground can be picked up with thru vias if required. I'll need to move things around a little to make room for larger ground surfaces that aren't connected.

Think TK provided the initial schematics for the Pod and Base unit interface. One question is about the two shunt capacitors on each line the base, are these actual physical chip capacitors or are the they equivalent capacitance as "seen" from that circuit position and used as an equivalent circuit model?

Anyway, looks like progress, but still lots of work ahead

Best,

[oz2cpu]

here you go, i think TK was the one to first provide the pinouts, he shared this file attached,

[oz2cpu]

PCIe connector measurements i use this attached
i do hope it fit :-)
in a few days i should know for sure

[oz2cpu]

here is the first idea of my 3D design for the two pods
two shells are screwed together
maybe i can 3D print 0-7 in one and 8-15 on the other, but it will be printed face down,
so maybe not that easy to make the text look good

[mawyatt]

Thanks for all the info. Think I found the actual connector Siglent is using, it's from Samtec. They indicate this connector is optimized for 50 ohms and may work OK at 75 ohms. Getting the signal off the base PCB and thru this connector in decent fashion to the support electronics in the scope may require some impedance tweaking of the base PCB networks, so likely some simulation and testing will be required. 

I like the idea of using the header connector on the end straddling the PCB rather than a right angle connector, this keeps the POD height to a minimum.

Best,

[oz2cpu]

>I like the idea of using the header connector on the end straddling the PCB rather than a right angle connector, this keeps the POD height to a minimum.

yes, and close to gnd alog the signal way , if any of the signals are needed at full speed,
better connect them with its own gnd wire twisted all the way to the test object,
that is why i picked the 2 x 8 way :-)

those PCB's are also on the way from JLC now, so i got some days to solve the pod 3D casing
just picked up a bunch of test hooks

[oz2cpu]

short video of 3D design

https://youtu.be/cS0elz5CfEk

latest files are also updated in the thingiverse folder
so you can 3D print them now and see how they look

[mawyatt]

Nice video!!

Let us know what you think of the test clips.

Best,

[oz2cpu]

i got this bunch of hooks for free from a local friend :-)
they are not the ultra tiny tip types
but they do fine for most things specially if there are test points

[oz2cpu]

I think about adding the one pin female and one wire to each for most flexible solution,
but maybe It is tempting to just add regular IDC type of connector like pictured here,
so if that must be possible, i need to open the sides a bit more, in the 3D pod design !

[oz2cpu]

3D printed parts for the PODS are now done and tested, see here

https://youtu.be/3Ttf7RSYKoU

[mawyatt]

Made a quick measurement of the scope input at the Digital Connector looking at the waveform attenuation based upon a simple resistive divider (100K with 1M scope probe). This works out to to be ~8.6K looking into the scope digital port line. Using this we made a quick spice model using a 3M 137 ohm twisted pair model, this has a velocity factor of 0.66 and a delay of 2ns (~400mm). As you can see the HP model parameter seem to produce a better overall waveform at the scope, and less perturbation to the input.

Best,

[oz2cpu]

thanks a bunch, this "reveal" why TK had great luck with the HP system he made :-)
the values simply trimmed it all perfect

[oz2cpu]

anyone playing with the logic analyzer today ?
I did not :-)
I played with the FFT mode, tested all sorts of frequency ranges,
all the way from 1Hz to 722MHz -5dB point,
I also learned about the full screen options of active features,
so it is very use full just to play a bit too.
amazing dynamic range and visual resolution this type of FFT can do,
see the 1Hz sine wave and its harmonics, now I just need to figure out what I can use this for,

[mawyatt]

thanks a bunch, this "reveal" why TK had great luck with the HP system he made :-)
the values simply trimmed it all perfect

Can you provide a link to this HP System? I've looked without success.

Best,

[oz2cpu]

here you go Mike,
see the bottom of the first post, main thread : Siglent SDS2000X Plus 

https://www.eevblog.com/forum/testgear/siglent-sds2000x-plus-coming/

[tautech]

here you go Mike,
see the bottom of the first post, main thread : Siglent SDS2000X Plus 

https://www.eevblog.com/forum/testgear/siglent-sds2000x-plus-coming/

[oz2cpu]

the 4 layer scope plug in PCB´s just arrived
now i need to se how easy it is to sand the front connector edge at 20 deg.

[oz2cpu]

PCB sanding tool, 3D printed and tested

[oz2cpu]

the sanding tool in action, works great, dont even think the screws are needed, the pcb go that tight in, and stay there just fine

[mawyatt]

Nice 

Best,

[oz2cpu]

a tiny tine adjustment of the 3D printed shell, it turns out the PCB and connector is NOT in centre,
6mm from bottom, 5 mm from top, and the lock grove is 1.4mm wide,
it also works, i see 2nS sample resolution on digital channels

[oz2cpu]

first 8ch tested :-)

[mawyatt]

Looks like you may be getting some "ringing" causing multiple edge detection? If so, likely due to the wire/cable/connector terminations.

Best,

[DL2XY]

This is how it looks on my diy adapter (see https://www.eevblog.com/forum/testgear/siglent-sds2000x-plus-coming/msg3094410/#msg3094410)



[ Specified attachment is not available ]
Only the inevitable 500 megasample jitter, even at 10000 sequences.

[oz2cpu]

look at my timebase, and I used the scopes own probe calibrator as the signal source :-)
it is not that sharp edged,
all i cared about was to verify all channels are right order,
I just put some random resistors in series, and tapped all channels along the way,
to give them all a little bit visual delay to identify them. tomorrow I use a faster, more stable signal source, and see if I can get alot less jitter.

[oz2cpu]

4 digital
1 analog
100ns/div

NO cables, on digital.

[oz2cpu]

here a lot of timebase settings, (this apply to all types of LA hardware, DIY and official hardware, it is a scope thing, confirmed)

the Digital got 2ns resolution (500MSa/s) so of course we expect the level change to be detected in 2ns steps...
however the clock to the digital sampler is NOT in phase or locked to the 2G samples the analog part uses !!!
so the jitter is random, and actually sometimes looking a bit funny depending on your curve frequency. (sample interference)

The same thing apply the other way : if you trigger on digital, they are now steady and locked to each other in fixed 2nS steps.
and now the analog curve gets "wide" from the random jitter. again it is 2nS wide, and it is only visible at speeds under 100nS/div.

the only way to fix this : is to lock the clocks together inside the scope design.

[oz2cpu]

lets find the perfect resistor values for the trigger levels to work correctly.
sorry still dont have 91k 0603 on stock
so i tried with 100k
and it is a little bit on the low side, see here

circuit:
120R 100k//8p2

https://youtu.be/H0SrdBlnq14

[oz2cpu]

OK found it..
all the other channels = 120R  100k // 8p2
D3 = 120R  87k // 8p2 now the trigger level is perfect
I used the digital level adjustment, and turned up, until the point where just a tiny pulse is visible, now it is very close to the 4.9V input signal
and it also show a better match in timing to this slow sine

I made 87k with 100k // 680k
this is not the way I like it, E48 series got 86k6 that is perfect

[bielec]

This has been a wonderful project and the engineering has been very well carried out.  I wonder if you would sell one of your pcb's to this man in Scotland?

[oz2cpu]

sure, the shop is open from next week, when the last pcb, the pod pcb´s arrive,
or you only need the scope pcb ? I got that one all ready.
I can also offer 3D printed parts real cheap, or send your the latest STL files, in case you got a 3D printer ?

you know JLC PCB, they are real cheap, I plan to sell the pcb´s at the double cost i payed, this way I have brake even when halve is sold,
I dont expect to see that many customers.

you got the SMD components ? or can get them easy locally ?

email : my user name, at gmail dot com

[2N3055]

here a lot of timebase settings, (this apply to all types of LA hardware, DIY and official hardware, it is a scope thing, confirmed)

the Digital got 2ns resolution (500MSa/s) so of course we expect the level change to be detected in 2ns steps...
however the clock to the digital sampler is NOT in phase or locked to the 2G samples the analog part uses !!!
so the jitter is random, and actually sometimes looking a bit funny depending on your curve frequency. (sample interference)

The same thing apply the other way : if you trigger on digital, they are now steady and locked to each other in fixed 2nS steps.
and now the analog curve gets "wide" from the random jitter. again it is 2nS wide, and it is only visible at speeds under 100nS/div.

the only way to fix this : is to lock the clocks together inside the scope design.

While you're at it, call Keysight and tell them to fix their scopes too....

[oz2cpu]

looks like the same 2nS digital resolution,
but see !! is the fixed :-) that is nice to see no random free running sub ps jitter
so this unit uses the same clock source,
how does it look, if you trigg on digital ? how is your analog looking ?

[rf-loop]

here a lot of timebase settings, (this apply to all types of LA hardware, DIY and official hardware, it is a scope thing, confirmed)

the Digital got 2ns resolution (500MSa/s) so of course we expect the level change to be detected in 2ns steps...
however the clock to the digital sampler is NOT in phase or locked to the 2G samples the analog part uses !!!
so the jitter is random, and actually sometimes looking a bit funny depending on your curve frequency. (sample interference)

The same thing apply the other way : if you trigger on digital, they are now steady and locked to each other in fixed 2nS steps.
and now the analog curve gets "wide" from the random jitter. again it is 2nS wide, and it is only visible at speeds under 100nS/div.

the only way to fix this : is to lock the clocks together inside the scope design.

Look like there is now some kind of misunderstanding about how oscilloscope works, how trigger works and how analog channel (yes only these) signal position is fine adjusted for minimal visible trigger jitter, as long as trigger is in analog channel. Btw, analog channels trigger engine is totally in digital side after ADC, fully and infinitely. But digital channels are just raw sampled after comparators, and just its 1/0 state is sampled.

And absolutely sure analog ADC and this digital channels sample use same clock. I do not believe, I know it. Period.

For  stop this bullshit spreading, please take pen and paper and analyze this and after 5 minutes you understand whu there exist random jitter. If you can not analyze it, then you need only believe when peoples who know, tell it. 3055 sure know it. Also I know.
Only problem is now your thinking and logical reasoning does not work properly. Where is this blind spot, you need solve it - or believe what others who know, say. 
Analog and digital side clock is same and samples synchronized.
Random jitter occurs and this is a natural and inevitable consequence of the operation of the system and is not even affected by the name of the manufacturer.

Btw, even with scope you can do some very simple demonstrations. Turn scope acquisition mode to slow. Turn display mode to Dots. After then use some different signals and also use single shots.
Do you find ANY single case when analog side and digital side do not stay hand in hand. No, there is not exceptions.

Also you need understand that analog side use fine positioning system based to fine interpolation between samples. But, digital side do not have this mechanism at all... because it can not do. Why, because there is not data for do it. Also this is true, independent of manufacturers. There is no manufacturer who can adjust something when there is no data for it. Only what can do for less jitter (based to this mechanism) is rise digital side sampling speed. It is very different when some may have 5GSa/s and one have 0.5Gsa/s. some manufactures have in some models same samplerate for digital and analog. Still there is is this jitter, and it is random. Inside one sample period edge can be where ever. If it is used for trig, then analog channel jitters relative to digital channel edge. Because true edge is randomly somewhere between these digital channel samples. But analog channel draw it, if there is more samples in this edge if you stop scope you can look where is true edge and then look how much digital side edge is in wrong place... think  carefully now why this digital edge is in wrong place... even when trigger was in digital channel. This is perhaps part of your blind point. With pen and paper you can easy see it. Think carefully what happen in analog side and digital side and how digital side trig.
Digital side do not trig to rising edge at all!!  Digital side trig to state! State may have changed in every position between previous and next sample. When sample state is changed, digital side generate trig. True state change can be just here or it can be just after previous sample. But same time analog side display where and how signal change (and if equal propagation delay with digital channel, same time). Now every turn it can be randomly where ever between these digital side samples. Random! Because external world is not locked to oscilloscope clock signal. (Random until you phaselock used test signal to oscilloscope sampling clock.)
If I have native english this is more easy to explain. But I have this FinChinglish.

[oz2cpu]

>stop this bullshit spreading

here where i come from, we try to talk nice, even if we dont agree

I would not call it BS, I just say : there is a free running clock on the digital 500MHz and another 2GHz on the analog,
since they are not locked in this unit, you get time jitter, when combining digital and analog and trig on one, and look at the other.
2nS is far from a real problem, all know that for sure.
but you need to go all the way down to 100ns/div for this not to bother your visual look and feel of your curves,
again : compleetly normal and there is a fundamental reason for this.

[rf-loop]

>stop this bullshit spreading

there is a free running clock on the digital 500MHz and another 2GHz on the analog,
since they are not locked in this unit, you get time jitter, when combining digital and analog and trig on one, and look at the other.

And still you continue this.

Where from you get this idea these clocks run wild.  ETA: I think this incorrect reasoning happen or can see here « Reply #45 on: Yesterday at 07:47:24 pm ».
Please think carefully why it is random. I have many times advice some small tools for correct this misunderstood.. paper and pen... run scope in dots mode... and run scope in slow acquisition mode so that every frame have only one acquisition. Watch these dots and watch these digital signal edges. Switch trig source between analog and digi ch. Use enough fast time scale (old term time base)  I hope some day blind spot get light.

 I can not understand what is base reason for this claim. ETA: (except if it is what can see in reply #45 what I just read more carefully)

Perhaps you can tell how much jitter is between these clock signals. Perhaps you can also tell where this jitter is added to this clock (this amount what we are now talking here). Source for both clocks is same. Amount of this jitter is and must be totally in different ballpark if think this 2ns sample interval time window and then external signal what can randomly be where ever inside this time window. This is main part of this jitter.
If you do not believe open it and measure these clocks.

Even when these clocks have some small jitter between each others (because in real world zero jitter is absolutely impossible than DC what do not exist in this universe) this is not reason for this random jitter we are talking now here.

[oz2cpu]

>Where from you get this idea these clocks run wild.  I can not understand what is base reason for this claim.

the sub ns sec jitter, the only way to explain it, (in my brain) is if the clocks are free running.
(and that case is the only thing we argue about :-)
I do agree i find it hard to belive they would design it like that,
it sounds smarter and cheaper to have only one clock source for the entire unit,
and again it is not a big practical problem, since most cases with digital and analog debugging at the same time,
you will ofcourse use a timebase at 100ns or slower

[DL2XY]

there is a free running clock on the digital 500MHz and another 2GHz on the analog,
since they are not locked in this unit, you get time jitter, when combining digital and analog and trig on one, and look at the other.

Just for proof this is not the case here are some crosslinked screenshots from the Siglent SDS2000X Plus thread:





All are made with signals derived from scope clock (internal awg) so they are phase coherent to aquisition.
There is no more jitter than a fews picoseconds, regardless if triggered on analog or digital channels.

[oz2cpu]

you are a GENIUS DL2XY DANKE !!
perfect experiment to prove this : this means i was WRONG and i am not afraid to say so.
so the final words on jitter : all clocks are in fact locked and from the same source, digital, analog and awg,
I did the same experiment as you and all is now super,
there is still jitter, but it is ALOT less, and it is fixed like shown here,

by the way, I dont understand how you made the first picture ?
you are clocking an 8 bit ripple counter ?

[DL2XY]

Thank you.

You can even use this method in practise, just clock your target system from internal awg (i did so for the walking bit pattern).
If i need higher clock rates than 10 Mhz i use the internal awg to synchronize my SDG6052, so i can create coherent signals up to 500Mhz.

73 Walter

[2N3055]

>stop this bullshit spreading

here where i come from, we try to talk nice, even if we dont agree

I would not call it BS, I just say : there is a free running clock on the digital 500MHz and another 2GHz on the analog,
since they are not locked in this unit, you get time jitter, when combining digital and analog and trig on one, and look at the other.
2nS is far from a real problem, all know that for sure.
but you need to go all the way down to 100ns/div for this not to bother your visual look and feel of your curves,
again : compleetly normal and there is a fundamental reason for this.

I agree, politeness is nice, but  you really should stop insisting repeating statements that are simply wrong, after being repeatedly told they are wrong.
There are no different clocks for digital and analog sampling inside scope. Period. And it is not an opinion. I know that.

What you see is artefact of analog channel correction for trigger point, difference in sampling clock for digital and analog, and sampling (timing errors) for discrete logic sampling between two asynchronous timing domains.

Keysight has same problem, but they are deciding to round up display to discrete steps, while Siglent shows you exactly how it would look if you were to lock analog CRT scope to a logic analyser.
In the end they both show same uncertainties. MSO from Picoscope goes even further, they don't even draw vertical edges, but a block that is as wide as uncertainty is.

Here is another screen from Keysight. Here we are triggering from D0.
You will see that analog signal indeed jitters around, and also that the very trigger point of sampled signal also jitters around. How can THAT be, if we are triggering on that very edge.

Explanation lies in how Keysight implements the engine. 

So what is better.  Keysight way where they are rounding timing information to show "pretty" display, or Siglent that shows you jitter between synchronous and asynchronous sampling (in regards to outside measured signal) ? They both show same uncertainty period, and if you see any artefacts on edges, you are trying to measure something too fast. So what is better?

Here is my opinion: They will both do the job of looking at the slow serial busses in the end.
But I prefer Siglent way, because it is exact representation of physical sampling processes as they are happening. It, in fact shows on the screen exact correlation of two clock domains and how the signal was sampled by scope digital channels correlated to input signal (represented by analog channel which is made synchronized to input by software algorithm)

PS: before posting this I realized DL2XY made great post proving this all by synchronizing input signal via using internal AWG.

[2N3055]

I threw together diagram that shows sampling:



Analog channels are sampled with clock that is synchronous to internal scope clock, but then interpolator adjusts them left and right to place them correctly at trigger time zero. That makes it synchronized to external signal on input. Digital channels stay at physical sample points, because they have no way to measure phase difference to input signal and make timing corrections.
So analog and digital signals will not be synchronous, and difference will be defined by correlation of frequency and phase off the both clock domains (external signal/scope clock).
It's magnitude will be defined by sampling clock and difference in sampling clock for analog and digital channels.

[oz2cpu]

thanks a lot 3055 for the nice drawing, I had the idea my post #57
could be the final of this one ?

maybe we could make an even better drawing ?
2 Ghz scope clock for analog
500 Mhz scope clock for digital
those two , we now know are locked together,
so this means anything we see on analog or digital channels, must happen in a clock transition,
now to the magic that confused at least only me :
my case was the incoming analog/digital signal was free running,
I had the idea BOTH analog and digitals where sampled at the SAME (but of course using their own speed 500/2G)
if I come with only one single pulse, its timing will differ on digital, versus analog,
not in fixed 2ns hops, but in anything random, under 2ns, from measurement.
that is, a bit funny if you think about it :-)

[2N3055]

thanks a lot 3055 for the nice drawing, I had the idea my post #57
could be the final of this one ?

maybe we could make an even better drawing ?
2 Ghz scope clock for analog
500 Mhz scope clock for digital
those two , we now know are locked together,
so this means anything we see on analog or digital channels, must happen in a clock transition,
now to the magic that confused at least only me :
my case was the incoming analog/digital signal was free running,
I had the idea BOTH analog and digitals where sampled at the SAME (but of course using their own speed 500/2G)
if I come with only one single pulse, its timing will differ on digital, versus analog,
not in fixed 2ns hops, but in anything random, under 2ns, from measurement.
that is, a bit funny if you think about it :-)

Well for the detailed drawing, that's a homework for you, I did mine.. 
But detailed diagram is not important. Scope can be put at timebase where both will be 500 MSps/sec and my diagram shows that particular condition, and also it makes it clearer.

As for the question, that is what I try to explain: both A/D converters (on analog CH) and latches after comparators (for digital CH) are sampled synchronously.

But trigger point on analog signal will be anywhere in between two samples. Look at my diagram.
Then in postprocessing, scope will declare that point 0 time (because scope is considering input signal the master, which it should).
Since digital channels are still aligned to scope clock, there will be skew between scope trigger point (zero time) and those edges.
And on every trigger that skew will be different.

So scope is actually trying hard to show you exactly where input signal was in correlation to scope digital sampling clock. It is not jitter, it is actual true representation at which point in time was every edge sampled. It is a diagram of correlation of outside signal periodicity and periodicity on internal sampling clock.

A small reading recomendation:

http://hparchive.com/Journals/HPJ-1997-04.pdf


Back in the olden days, we used synchronous logic analyzers, that were clocked from DUT, to solve this problem.
For this type of asynchronous sampling LA (like all MSO scopes today are) you get edge timing limits that need to be taken into consideration. For protocol analysis, 10X oversampling will work quite well, which means that you should be able to decode quite fast serial protocols with 500 MPs/s.
For accurate timing analysis, you should use analog channels. In which case you can get very good results, and resolve less than 100 of picosecond timing.
Not bad for a inexpensive scope...

[oz2cpu]

EXACTLY !
and for the record, I did update my "complain" video, and i also updated the bug report post.
thanks again for helping with the deep diggin, now I need to order a new signal generator,
since this scope reveal other unwanted artifacts from my old, I am looking at SDG6022X

[rf-loop]

Keysight has same problem, but they are deciding to round up display to discrete steps, while Siglent shows you exactly how it would look if you were to lock analog CRT scope to a logic analyser.
In the end they both show same uncertainties. MSO from Picoscope goes even further, they don't even draw vertical edges, but a block that is as wide as uncertainty is.

Here is another screen from Keysight. Here we are triggering from D0.
You will see that analog signal indeed jitters around, and also that the very trigger point of sampled signal also jitters around. How can THAT be, if we are triggering on that very edge.

It is weird. Really weird.

Then a small side jump next to the thing
MegaZoom IV give many advantages over many other scopes but...

This article (Keysight blog)
https://keysightoscilloscopes.wordpress.com/category/oscilloscope-triggering/

is somehow fun to read... and when look publisher and authors... there is also some drawings.. and note that this time "all" was Megazoom IV. 

This not reason and partially nonsense but... trigger in analog side is also ancient analog sidepathway / comparator based system. Due to megazoom IV advantages they need advertise these advantages and hype these and then keep mouth closed about other things as example that it have conventional analog side pathway trigger system - if I have understood right.
I have not seen any sales brochure where is imagined Megazoom IV where is also displayed where from trigger "bloc"get signal... in every image this line is missing.
Of course well done analog side pathway trigger system can be good/very good (and in top - expensive. Perhaps LeCroy know how expensive)...
Analog trigger can also see things what full digital side trigger can not see at all, both systems have some but different disadvantages. Simplest example, levels what are over ADC FS, analog trigger can still work. Also, analog side pathway trigger is never ever fooled by alias! But, other hand it may get different signal shape and phase. Digital side digital trigger engine do not know if ADC output is ADC produced alias (down conversion) or real.

By Colin F. Mattsonin Oscilloscope Triggering, OscilloscopesJuly 27, 2016: "How It Works

Most real-time oscilloscopes have an “analog” trigger system.  This system is actually a mishmash of analog circuitry and digital counters but it relies on input from analog comparators fed from the scope pre-amp.  Some oscilloscopes now feature a “digital” trigger, meaning that the trigger system is entirely digital and is fed with integer data from the ADC output.  Both types of systems perform the same function; evaluating whether or not all of the configured trigger conditions are met at a given moment in time.  Because fully digital trigger systems are fairly rare, we’ll focus on analog trigger systems."

Is it possible they fine adjust analog signal even when trigger is from digital channel. If they do this... perhaps there is more artists than engineers... for "nice looking images". Without further tests this can not know.
Maybe it’s not even very interesting. If truth do not look all nice do not still hide it or bend it looking more nice, as long as we talk test and measurements instruments!

[mawyatt]

The old analog Tektronix scopes had the best trigger system of any available scope at the time, much better than HP. Like much of the old Tektronix analog scopes, this trigger system was a masterpiece of engineering (like transistor ft doubler preamp for example) and utilized ECL gates as fast analog differential limiting amplifiers in the trigger system because of the ECL transistor speed. I doubt much improvement over this superb analog based trigger system over the years other than use of higher ft transistors for faster triggering.

Does any scope have both digital and analog triggering capability?

Best,

[oz2cpu]

the last two posts super interesting, but now we are doing it again.. change topic in a thread :-)
how about we find out how the trigger is really made in the Siglent SDS2000 scope ? and continue in the Siglent scope thread ?
since this scope got FPGA front end to handle the ADC's I would guess it is all done in fpga "hardware"

[tautech]

the last two posts super interesting, but now we are doing it again.. change topic in a thread :-)
how about we find out how the trigger is really made in the Siglent SDS2000 scope ? and continue in the Siglent scope thread ?
since this scope got FPGA front end to handle the ADC's I would guess it is all done in fpga "hardware"

Trigger discussion is highly relevant to this thread and it's already been disclosed the LA trigger path is different to the analog input digital trigger path where instead the LA path uses comparators.

As has already been pointed out the comparator only needs see its threshold has been met not at what level so combined with the slower LA sampling rate that introduces the timing uncertainties we see as jitter.
It's not like this is a big deal when investigating analog to digital signal conversion when using a LA trigger when we have a deep memory scope as we can record the analog events leading up to the digital trigger.

[DL2XY]

There is another point to take into account doing timing analyses:
The trigger level is not absolute, each comparator has a hysteresis of about 650mV (relative to input of 10:1 divider).
Depending on rise and fall times that leads to additional delays.

[rf-loop]

There is another point to take into account doing timing analyses:
The trigger level is not absolute, each comparator has a hysteresis of about 650mV (relative to input of 10:1 divider).
Depending on rise and fall times that leads to additional delays.

Handling hysteresis is different in analog channels and digital channels. In analog channel hysteresis window (wide or narrow hysteresis, depending settings) is always "before" defined trigger level. If user change rising edge trig to falling edge, trig level point is same but hysteresis is moved from downside to upside.
 
But as far as I know example usual PECL comparators have just HW fixed Vhysteresis (usually Vhys is settable example using external resistor). Ordinarily threshold level "0" is center of hysteresis window, so +Vhys/2 is above the threshold level and -Vhys/2 is below the threshold level.
This is very different in analog channel trigger. In rising direction of trig, example edge trig, Vhys is below the threshold and for falling direction of trig Vhys is above the threshold level. In analog side also amount of Vhys is proportional, and even more, we have there two user settable proportional amount of hysteresis. (amount of Vhys is proportional mean that it is some amount from used V/div. I do not remember SDS2000X+ but some scope may have example narrow hys 0.3div and wide hys 0.8div (SDS1000X-E series) explained here but unfortunately by Finnish language what is my native lang. https://siglent.fi/oskilloskooppi-digital-trigger-system-siglent.html )

So, example, rising edge, if we set analog channel trig level to 1.5V and digital channels threshold level to 1.5V  trig position in time axis is different. 
Before edge analog is below [Trig level - Vhys].  And Digital side signal is below [Vthreshold - Vhys/2].
Now when signal  start rise in analog side first it cross over [Triglevel - Vhys] and after then it reach [Trig level], result is "Trig"

If trigger is in Digital side. Signal start rise and first it cross over [Threshold level - Vhys/2]  after then come [threshold level] but nothing happen... after then it cross over [threshold level + Vhys/2] and then result is "Trig". 
Time difference depend this rising time ( pitch angle).

So, yes there is difference and user need understand it if he is working with slow digital side rising times and are looking things in nanoseconds range.  Btw, how much it is if rising slope is slow 10ns.   

User need just understand this for avoid some traps, as is always important what ever feature is used. "Know your tools..." and so on.



About DIY  LA probe. What is thickness  of gold (and what alloy)  in contacts because this is for frequent plug in - plug out use.
Also, PCB material is important. If it is glass fiber etc.. its edge, even if it have some angle, may cause grinding in connector contacts surface. Perhaps example teflon do not so easy wear and tear this connector. Also contact surface gold or other metal alloys are different for resist wear and tear + corrosion + thermal EMF (what is not important just in this case). But it need resist wear and tear and corrosion/oxidation.  Example PCI-E connectors are not at all designed for continuous and frequent plug in plug out. It can last but need use carefully and cable connector need take care about avoid this PCI-E connector wearing.


Cable. (I do not have any idea about prices, but technically interesting)

There is also available many small dimension coaxial cables manufactured example for medical use. No need be just flat ribbon coaxial.. just example multiple coaxial in soft very flexible (also in low temperatures) silicon etc tube..

Example Coonerwire  http://www.coonerwire.com/mini-coax/  CW2040-3695 F  what is 95ohm coaxial with 0.062 O.D. and 13.5pF capacitance. Or CW2040-3650 F what is 50 ohm, 29.5pF  O.D  1mm aka 0.039"

And whole catalog top quality cables  http://www.coonerwire.com/cooner_catalog_rev9-8.pdf

Some wires are perhaps bit expensive, example pure gold cables

[oz2cpu]

>User need just understand this for avoid some traps, as is always important what ever feature is used. "Know your tools..." and so on.

EXACTLY and that is why it is very smart we deep dive into all this,
using the LA alone, versus together with digital, what happens, and most important why,
this way we all get a smarter, faster, and more happy day,
next time we need to debug some real life stuff :-)

[rf-loop]

>User need just understand this for avoid some traps, as is always important what ever feature is used. "Know your tools..." and so on.

EXACTLY and that is why it is very smart we deep dive into all this,
using the LA alone, versus together with digital, what happens, and most important why,
this way we all get a smarter, faster, and more happy day,
next time we need to debug some real life stuff :-)

Y E S

[mawyatt]

Here's the latest concept we're looking into. This features an expansion of the base connector case to the MSO to allow dual 16 pin 2 row headers, one for digital inputs 0-7 and the other for 8-15. These are designed to support 8 pairs of twisted ribbon cable, or a common 16 wire ribbon cable with GSGS type configuration.

With this configuration the base case can remain attached to the MSO and the ribbon cables plugged into the base header connectors, also allows different cable types or lengths to be used between the Base and the Probe POD. The POD supports a 16 pin header with 8 digital lines, and 8 ground lines, but also can directly support single lines with a 1 pin header (Dupont type).

Should be a very flexible architecture allowing experimenting with different cable types & lengths. We've just ordered, per recommendation by oz2cpu, a 3D printer and downloaded Fusion 360 to try and "get up to speed" with 3D modeling and printing, not sure how long this will take before any actual 3D printed cases emerge since absolutely no prior experience with any of this 3D stuff. Also, ordered a few twisted pair ribbon cable types to evaluate and measure characteristics, along with various header types, connector pins & crimping tools.

Custom PCBs for the Base and PODs are not a problem or big delay, and will be flexible enough to allow variations and maintain good signal integrity.

Anyway, putting this out for others to comment and maybe even consider.

[xandmann]

According to a test report regarding PCIE connectors from Samtec, the connector in question will withstand (depending on the angle of pull) between 300-600 mating cycles and a 90 deg pull force of 50 kg.
So using "bare PCB" adapter solutions without 3D printed casing shouldn't be a problem, however depending on ones bench setup frequent insertion/removal might cause problems in the long run.

[oz2cpu]

i prefer, and suggest, and recommend to use some sort of steering of the pcb into the scope LA socket,
this way it goes in correctly, stay in right angles, and this way the scope part will live longest possible,
the work is worth it, if anyone like fusion files, or step files, or stl files for free, simple PM me.
AND you are also welcome to get gerber files or altium design files

[tautech]

i prefer, and suggest, and recommend to use some sort of steering of the pcb into the scope LA socket,
this way it goes in correctly, stay in right angles, and this way the scope part will live longest possible,
the work is worth it, if anyone like fusion files, or step files, or stl files for free, simple PM me.
AND you are also welcome to get gerber files or altium design files

I suggest you write up the 3d part of the project and add the files here:
https://www.eevblog.com/forum/testgear/replacement-knobs-feet-and-fittings-for-test-equipment/
Don't forget to add a link back to this thread. 

[oz2cpu]

thanks for the link, I update my files at thingiverse, and see if that site also accept gerber zips

[tautech]

thanks for the link, I update my files at thingiverse, and see if that site also accept gerber zips

Just add the links into your posts.

[oz2cpu]

i stole your idea, and put all important external links to topic post one, this is a good way to add higher user experience
i wish more people will do this, lets recommend all to do that

[oz2cpu]

to Mike, thanks for your great drawings about test pod design, and about putting all 16ch into one pod for test leads beakeout
at first glance it looks very smart, and your cables to scope, can be more nice this way,
but lets think about it :
all other brands i have used and can think about, are using a 2 x 8 ch pod design, with a split cable configuration to the scope,
so why are they doing it this way ?
maybe the reason is :
if you only need 1-4 ch, you use the analog ch.
if you need 8 digital, you use one pod,
if the pcb is rather large and 4 bits are located in one area far away from 4 other,
you can use analog and digital, this way the single wire test leads to the pcb can still be short, better for signal integrity,

IF you need 16 ch digital ??
most likely they are not in the same area but in two or more locations on a large pcb,
so it will be an advantage if you got 2 x 8 ch pods, so each single wire test lead can be as short as possible,

am i wrong ?
PS: JCL say the pod pcb is send several days ago, still not here yet

[mawyatt]

Please review the sketch again, the design uses two PODs but only one for bit 0-7 is shown. The other POD would be for bit 8-15, but not shown. The PODs have 16 pin header connectors for the Probes leads and the interface cable which can be a regular 16 wire ribbon cable with GSGSGSGSGSGSGSGS, or 8 twisted pairs, or 8 coaxial cables and interchangeable with different lengths. The base unit interfaces with the scope and has two 16 pin headers connectors for the 0-7 and 8-15 separate cable interfaces. Also note that you can forgo the use of the PODs and directly connect the Probe wires to the base if you want, but this doesn't have the network for the probe lead interface with the high value series resistor, so over voltage protection would be compromised.

I'm not too concerned about the header connectors impedance levels (using your idea of end PCB mount) and mismatch adding much additional signal corruption, but this needs to be addressed with some measurements and maybe simulations to verify.

In summery you have two PODS and two interface cables to the Base, all have connectors for added flexibility in cable types, length and placement.

Best,

[oz2cpu]

thanks for the correction Mike, your are right.
another advantage to make it this way : is most likely normal of the shelf IDC cables could be used,
how much is the special twisted types better, over straight flat normal, at this speed, and short length

[rf-loop]

at this speed,

can you specify it.
Fundamental square freq what ever is not important but what are edges speed and not even what is probe/interface speed. Meaningful is this signal speed where probe is connected. It makes most of bad things - if any, where cross talk is one of very serious problem what need take seriously. Even when signal pulse stream is 1 or 10MHz but if DUT risetime is in ns class it is easy cross talking even over SGSGSG... flat ribbon. It need think, scope LA probes are connected to unknown signal where can be "what ever" except over voltage.  Cross talks are very extremely annoying when they exist and can rotten measurements. Naturally one solution is reject edge speeds what can go to cable. Older SDS1000X+ model have ribbon LA probe cable SGSGSGSG...  and it cross talk easy with fast edges. I think it is same SPL1016 probe what is today for SDS1000X-E what have external probe interface to scope but probe itself is same.

[mawyatt]

thanks for the correction Mike, your are right.
another advantage to make it this way : is most likely normal of the shelf IDC cables could be used,
how much is the special twisted types better, over straight flat normal, at this speed, and short length

The ribbon cable will be the worst, then IDC, with ribbon twisted pair next and the coaxial cable the best I suspect. Having this type setup makes it relatively easy to do a comparison of the different cable types. We've ordered a couple different types of ribbon twisted pair, and the ribbon, but don't have a low cost source for the coaxial cables. Another type of ribbon twisted pair has a shield around the entire ribbon, this should be better than the unshielded ribbon twisted pair I believe. Haven't found a low cost source for these either.

https://www.digikey.com/en/products/detail/3m/1785%2F60%2520100SF/1190424?utm_adgroup=Flat%20Ribbon%20Cables&utm_source=google&utm_medium=cpc&utm_campaign=Shopping_Product_Cables%2C%20Wires&utm_term=&utm_content=Flat%20Ribbon%20Cables&gclid=CjwKCAjw9MuCBhBUEiwAbDZ-7lfmaQmWYfxxI9q57kl3Y86O2jPrS2SEoI_EODoIM_kYkceup0tjxRoCGrEQAvD_BwE

We need to do some 3D EM modeling of the end feed header & connector to get an idea of what this looks like electrically. A little Red Neck Engineering [term for us folks born is Southern USA that like beer ] and without any proper 3D EM tools, gives a very crude estimate of the end feed header and connector as a small section of transmission line of ~180 ohms, with a delay of ~150ps. Here's a crude estimate of the waveforms as "seen" by the Scope, the Probe, and Ideal Signal Source.

As a grad student we would do anything for a beer, never outgrew this limitation

Best,


Edit: Added 2nd plot which shows the effects of the input Probe lead as ~270nH based upon a 26AWG wire of ~200mm long, inductance estimated based upon Grover's Single Wire Equation. Scope waveform shows ~3.8ns mid-point delay.
 

[oz2cpu]

mike ? did you look into the math about twisted pair cables ?


https://www.allaboutcircuits.com/tools/twisted-pair-impedance-calculator/

[mawyatt]

Yes, we've looked into the math and the data sheets from 3M for the twisted pair. The single wire as used for the Probe lead wire and the Ground lead wire must be estimated from the self inductance of a single wire not a twisted pair tho.

Here' a simplified model we're using for the LA, later the PCB characteristics for the Base unit and the POD will be included, which will be followed up with some measurements. Note that the Scope PCIE connector and other details haven't been included yet. The model will be augmented as needed with additional components and parameters to better reflect the actual hardware envisioned as we move forward.

Also, working towards getting to a level where we can use 3D modeling and printing to create this structure, so will take some time since no prior experience with either.

Edit: Here's a controlled impedance cable "back of the envelope" concept (when you don't have the proper cables readily available) we've wanted to try but never had the time. Should show a much better signal to signal coupling and a lower intrinsic impedance approaching what a proper coaxial line would produce over a single ribbon cable. Uses a standard ribbon cable with SGSG orientation, but with another ribbon cable on top and bottom glued into the groves between the wires of the main center ribbon cable. This should approximate a coaxial cable and have an impedance of ~80 ohms as shown. Might be worth playing around with since most folks have the standard ribbon cable available and it's inexpensive, you could shroud the 3 ribbon cables with some thin heat shrink to make it more durable and look nicer.

Best,

[tautech]

Mike, when I get a chance with a ~2ns pulse source and 1 GHz scope I'll scope a SPL2016 channel or 2 for you to compare against your simulations.
Should be later today after I've ticked a few other jobs off.

[tautech]

Mike, when I get a chance with a ~2ns pulse source and 1 GHz scope I'll scope a SPL2016 channel or 2 for you to compare against your simulations.
Should be later today after I've ticked a few other jobs off.

20ns pulse with 2ns risetime ex SDG6022X.
3.3Vpp into SPL2016 grabbers.
Measurement at SPL2016 PCIe plug with SDS5104X 10x 500 MHz probes. Scope floated to use SPL2016 Gnd path for probe reference.

[mawyatt]

Mike, when I get a chance with a ~2ns pulse source and 1 GHz scope I'll scope a SPL2016 channel or 2 for you to compare against your simulations.
Should be later today after I've ticked a few other jobs off.

20ns pulse with 2ns risetime ex SDG6022X.
3.3Vpp into SPL2016 grabbers.
Measurement at SPL2016 PCIe plug with SDS5104X 10x 500 MHz probes. Scope floated to use SPL2016 Gnd path for probe reference.

Thanks Rob, I'll need to try an create a model for the Siglent SPL2016.

The impedance of the coaxial lines is lower, likely around 50~60 ohms, but how long are the coaxial lines, and how long are the probe leads and ground lead? What is the tip capacitance of the scope probe used, I'll need to include that to estimate the effects of the scope probe, and was this measured with the SPL2016 plugged into the scope or stand alone? From the looks of the pulse shape it's stand alone so isn't getting the full influence of the PCIE connector in the scope and the loading effects.

All this will help get a better estimate of the SPL2016 behavior.

Edit: Also what is the DCR reading from LA probe tip to the PCIE PCB edge connector?

Cheers,

[mawyatt]

[ Specified attachment is not available ]

Mike, when I get a chance with a ~2ns pulse source and 1 GHz scope I'll scope a SPL2016 channel or 2 for you to compare against your simulations.
Should be later today after I've ticked a few other jobs off.

20ns pulse with 2ns risetime ex SDG6022X.
3.3Vpp into SPL2016 grabbers.
Measurement at SPL2016 PCIe plug with SDS5104X 10x 500 MHz probes. Scope floated to use SPL2016 Gnd path for probe reference.

Rob,

After some analysis and estimating what we "think" Silgent has done with the SPL2016, here's a first cut at simulating such per your measurement.

Best,

[tautech]

I'll need to try an create a model for the Siglent SPL2016.

The impedance of the coaxial lines is lower, likely around 50~60 ohms, but how long are the coaxial lines,

1150mm from PCIe plug to lead breakout connector.

and how long are the probe leads and ground lead?

A further 200mm, 150mm

What is the tip capacitance of the scope probe used,

Apparently 11pF
https://siglentna.com/wp-content/uploads/dlm_uploads/2020/02/SP3025A_3050A_Users_Guide.pdf
Have SAP1000 with 1.2pF if you need another measurement with that.
https://siglentna.com/product/active-probe/

I'll need to include that to estimate the effects of the scope probe, and was this measured with the SPL2016 plugged into the scope or stand alone?

Stand alone.

Also what is the DCR reading from LA probe tip to the PCIE PCB edge connector?

91.1k

[oz2cpu]

91k1 ?? did you double check the trigger levels ? at super low speed ?
and a super high speed ?

my unit is more correctly triggering at the right spot with 120R + 86k6 // 8p2

[mawyatt]

Rob,

Thanks for the data, here's what we came up with as a quick estimate model of the LA. The Digital Input pulse was manipulated to try and create what we think the actual pulse to the LA looks like, and show the offset as shown on your DSO measured trace above.

The Digital Probe wire self inductance is based upon 200 & 150mm of #26 AWG wire, the 1100mm coaxial cable (shown as twisted pair in schematic) is modeled as having a Zo of 45 ohms and delay of 6.1ns based upon a velocity factor of 60%. Later we'll need to see how the twisted pair cable (and ribbon) rather than the coaxial cable effects these simulations.

Still slowly working my way thru the 3D modeling tools, and waiting for the 3D printer to ship. Custom PCBs are being developed and hopefully at some point will be able to create a 3D printed base and POD units using connectors for the Base to POD twisted pair cable (and ribbon), maybe even a coaxial version if a low cost cable can be acquired.

BTW we had to remove the models for the connectors used for the Probe lead interface, and the POD to Base for the coaxial cable interface. They were causing convergence and simulation artifacts (problem with transmission line simulations). Rather than fiddle with the simulation parameters and integration methods, we just removed the models knowing from experience they won't have much effect on the results, later as we fine tune things we may reintroduce these connector models as a verification check.

Anyway, here's what we've got so far.

Best,

[oz2cpu]

finally got a nice stack of POD pcb's today
they fit perfectly into the 3D printed shells

now i pack and ship to the first one :-)

[mawyatt]

Nice 

Best,

[oz2cpu]

YES it is to you.. I also packed a stribe og the special 86k6 resistors, as i said with this value (together with 120 ohm)
I get the most accurate trigger point
I think delay time, and match is much more relevant, but hey, let also get the triger point right if it is that easy

[oz2cpu]

latest update of how to solder,
in your emails I refer to this page for latest info,
this way i only need to update one location

[oz2cpu]

I just got an idea, had a bunch of DVI cables, and took a look inside,
wow perfect, 4 pair of perfect thickness wires, and 5 even thinner wires, perfect for electronic DIY :-)
50cm cables

[oz2cpu]

and here is a little video
https://youtu.be/aK7hYr5Y-6Y

when more people get more used to working with the LA
I love to hear from you,
I recommend to turn deskew down to zero if you only use digital channels.
since a deskew setting will move all digitals, even if triggering on digital, and only showing digital,
this is think is a bit odd.

but ofcourse if you need to combine digital with analog, you need to dial it in,
my set need 13ns (50cm wires)

[Jeff C]

Wow, great idea with the DVI cable! Unfortunately I just threw out about 20 50 foot long parallel cables at work.   
I bet those would have worked out nicely. I guess I’ll have to see if there are any other unused ones still left 

[oz2cpu]

one of my friends said also look inside HDMI and Displayport cables, they should also contain 4 twisted pairs and a bunch of thinner single wires,
however i dont like to trash this type, since we use them for our PC stuff,
VGA cables are no good, the video wires are too thick and there are only 3 of them, and the rest of the signal wires are too thinn, for this project,
but could be perfect for other projects, so have a look in the electronic dumpster near you :-)

[mawyatt]

Nice 

We've used some Cat5 cable before which is small (~AWG 26) twisted pair but this was for precision analog use, it's solid copper and much too stiff for probe use. The 3M flat twisted ribbon type is smaller with AWG 28 wires (stranded) and flexible.

Best,

[natman69]

I agree that ethernet solid cables are too rigid for probe use but they can come also in stranded and very flexible versions with AWG 24-26. They are cheap and available in every shop.

Will this DIY probe be available as a kit? Any plan to sell it to eevblog users?

Anyway, really thank you for sharing this project!

[oz2cpu]

>Will this DIY probe be available as a kit? Any plan to sell it to eevblog users?

sure, see post 1
it is actually just PM me if interested :-)
right now the first few kits are send out,
during next week the design is expected to be fully approved
and i start shipping the rest, i still have pcb's stocked
i sell them real cheap .
have you smd parts ?
solder skils ?
3D printer ?
if not I can help with that too, for a little extra fee,
but the cables and test hooks, you need to get and solder your self.

YES Ethernet cables do come in flexible cores, but they are still a bit too thick
and to my experience not that good for soldering, the plastic melts too easy

[oz2cpu]

latest news, only a few are left now :

All the 3 loose pcbs = 10$
(the 4 layer scope pcb is sanded to correct connector end angle)

option, all the smd parts and the pin rows mounted, add 10$

option, all the 3D printed parts and screws, add 10$
(STL files are for free, incase you got a 3D printer or know one locally)

postage 5$, untracked, no insurance.

twisted pair cables, not included
(i recommend to use DVI cables, perfect diameter for the job, cut all wires exactly 50cm long)
twisted pair soldering, you need to do this your self.
test hooks with small female connectors, not included, see ebay and similar.

[FrancisM]

@ oz2cpu,

PM sent

[oz2cpu]

thanks FransisM all done, packed and send..
To any one else. mail via this system dont seem to be working at the moment, nothing show up, and no notifications too,
so please use normal emails : my username at gmail dot com

[Bad_Driver]

Good Morning OZ2CPU,

yesterday the PCBs arrived! Looks very good! I'm impressed by your SMD soldering capabilities, I tried some 8050 yesterday and two jumped into Nirwana ....
I need much more practice.... 
Unfortunately my 3D printer isn't working anymore. Last part I have finished was your SDS2000x+ blind plug, fits perfect!
After long investigations and part changing it seem to be the thermistor on the hot end. Now I'm awaiting a DuPont crimp tool from Aliexpress
for final repair. I keep you informed when I got the probes running, the tips are still on their way.

Thank you very much for this great piece of engineering! Keep you informed about my progress.

[mawyatt]

Haven't had time to do much with the LA since another project has taken over our available time, but hope to get back on this soon.

However, we can verify that Thomas (oz2cpu) LA Probe works well with standard 10 line ribbon cable (8 active, 2 ground), the twisted pair cable we have is a little too wide so used ribbon cable instead. Don't have a high speed pulse generator, but did verify that using a sine wave input from a AWG the Probe works to ~100MHz with ribbon. You do "see" a small amount of crosstalk, but that's expected, with twisted pair the crosstalk should be eliminated. Also can verify the 3D files print nicely.

Still waiting for a proper crimp tool and doublewide 16 connector "shells" for Dupont connector pins, so just used a single wide 8 "shell" and soldered the connector pins. As shown this supports the 8 active lines, and the ground lines are just a single Dupont connector.

Anyway, hat's off to Thomas (oz2cpu) for developing this DIY PA Probe for the Siglent Scope and making it available to others  

Best,

Mike

[FrancisM]

I acquired my 2104x+ three months ago and was surprised to discover that all the active parts for the LA were already inside the scope. Being a hobbyist and newly retired, I found it interesting as I never used myself such a piece of gear. Too expensive at the time.
I asked Thomas (oz2cpu) for the pcbs and all the parts he could provide.

In the mean time, I had to activate the needed option. I spent some time to dig into a thread about it and found all I had need for.
It was way more easy than expected and I ended up with a fully liberated scope !!!
I also built a test jig MCU based to have something to play with. I started with the PIC16F84 at it's beginning and now, mostly use PIC18F series wich satisfy my needs. Just a single pulse on each bit of two IO ports in a loop, to be sure I haven't mixed things up.

A smart guy made the soldering job of the tiny parts for me. I just had to solder the wires and close the boxes.
It worked like a charm at start.
The nice thing is I can see both digital and analog level of the same pulse.
I had some fun playing with the trigger and the options available.

Next step will be troubleshooting of a Z80 cpu board from the eighties. It fails to control water temperature in a coffee machine.

Thomas, without your offer wich was a bargain, the LA would have never been used on my scope. Some tens of MHz and half a meter length is all I have need for. It won't have an every day use so the official probe wasn't an option.

Thanks for all your effort, 
Francis

[oz2cpu]

Fantastic looks like you nailed it :-)
did you try to use the SKEW settings ?
with this you can trim the LA delay to match that analog channels

[techneut]

I was looking for cables and came across a scart cable. In it are 6 small flexible coax cables 50 Ohm. Is it worth the trouble to strip this cable and use them or is it not any better than twisted pairs? I would probebly need to change the 120 Ohm resistor value?

[oz2cpu]

scart coax is 75 ohm, so yes, all 120 ohm, needs to be 75
this way each side of the coax is terminated with 75, and you should expect as little as possible ringing, and better timing.
I prefer to use a high impedance as possible, twisted pair is about 120 ohm, and this way you load the signal source less,
that is also what you want.

[oz2cpu]

LATEST NEWS : MY STOCK IS EMPTY.
I DO NOT PLAN TO MAKE AND SELL MORE.
ALTIUM AND GERBER FILES ARE NOW IN THE THINGIVERSE LINK.

MAKE PCB and 3D files for OWN private use is alowed.
MAKE and sell PCB or 3D files, or fully assembled product, ONLY alowed if the sale price ONLY cover actual expenses.
it is NOT alowed to modify this design and distribute any part of it as your own.

[techneut]

scart coax is 75 ohm, so yes, all 120 ohm, needs to be 75
this way each side of the coax is terminated with 75, and you should expect as little as possible ringing, and better timing.
I prefer to use a high impedance as possible, twisted pair is about 120 ohm, and this way you load the signal source less,
that is also what you want.

That is what I expected 75 Ohm but I used the TDR with a variable resistor at the end of the cable and it was 50 Ohm. For analog video (< 5MHz) it doesn't realy matter. The BNC's used in analog video are also 50 Ohms. Only with SDi (540 MHz and higher) came the 75 Ohm BNC.

[FrancisM]

Thomas,

I learned what deskew is with my first digital scope some years ago. And I saw you using it while testing your probe earlier in this thread.
A friend of mine is amused to tell me that most of my gear is running close to DC, so I will leave it at 0ns.

This morning, I made some further testing on a Z80 cpu board. And as almost always, it started with a bad electolytic on the PSU. The +5V is a buck converter (L4960) and it's output cap measured less than one tenth it's original value, not speaking about esr. There was a lot of garbage on top of the 5V and it's probably the only issue. After replacement, the ripple was down to a decent value. The thing runs at 100kHz and I used a Panasonic FR.
So far, so good.

I was told the board fails to read temperature of a sensor. I can see an ADC0844 and some opamps connected at it's inputs. There's a span adjustment like in the datasheet and the opamps make the zero shift. It's a four layer board and I have no manual but the sensor seems to be connected to ch1 and ch2 through two opamps.

I connected your probe to the ADC data and control lines. Once triggered, the timings are clean but a read always outputs a 0FFh even with the sensor(PTC) connected. I then triggered on a write to get the mux mode control byte. It reads 04h wich is not what I expected. It translates to channel 1 in single ended mode while I thougt it to be in diff mode. The board doesn't seem to initialize as it should, probably an external missing stimuli. It will be replaced where it comes from with everything connected to it.

I had fun playing with my scope.

All the best,
Francis

[oz2cpu]

great, yes Z80 speeds is quite a facter away from this scope capeabilities,
but you are having fun, and learn how to use it as hardware and software debugger,
the more you dig into the z80 board, you be amazed how easy it is to find and fix all the problems.

[pzw]

I guess I was one of the lucky people getting one of the last sets! The PCBs look great, and well assembled!
One small hint for whoever will decide to make their own PCB; The inner layers of the PCB with the edge connector will be exposed when the edge is sanded under the correct angle. Not that it will create any issue, since I do not see how the exposed copper can short out anything. But if the internal layers are made about 1.5 - 2.0mm shorter at the edge connector end, this inner layer will never be exposed.

Now I am on the hunt for an old DVI cable, or maybe I just need to buy a new one ;-) .

Thanks again to @on2cpu for the nice PCBs and quick shipment!

[oz2cpu]

Fantastic usefull comment
if anyone like to take this up in the near future
and maybe dont own an Altium license, just pm me,
all files , gerber, and altium, are in the thingiverse link.

[techneut]

My pcb's arrived today and they are looking good. I'm waiting for the slow boat from China for the components and in the mean time checking out other scart cables for coax. We still have a lot of them at work.

[tautech]

Spotted in another thread is a better description of flat ribbon coax cables like OEM's use for these LA probes:
Google: micro-coaxial ribbon cable

Lots out there and will be interesting to see what motivated hunters of such products can find. 

[oz2cpu]

thanks for the hint, did a little googling :-) looks like it is clearly possible to get very thinn coax, and even in ribbon style,
however  : expect it will be a lot more work to hand solder, lower impedance..
and a lot more expensive / hard to get.
with the twisted pair : easy to get, chep, and easy to solder, and there is no detectable crosstalk..

[oz2cpu]

NEW updated files :

the scope plug in pcb is now in V2.0
files are at the thingiverse link

V2.0 released 16 may 2021
 inner layers pulled back at gold finger ends,
 this way gnd copper will not be exposed when edge milled.
 0R resistor removed, the idea with this resistor : to be able to use the plug in pcb alone,
 if this feature is needed, use V1.0

[mawyatt]

Great work!!

A couple notes regarding the newer PCBs. Don't see a spot for the lead cap in the POD PCB, this is in parallel with the high value resistor. When we assembled your POD PCB we had to stack the cap on top of the resistor, not so easy with 0603 SMDs. Also the terminating resistor at the scope side BASE doesn't actually terminate the transmission line since the input to the scope is relatively high Z. In fact the input terminating resistor doesn't do this either since the input probe lead is a large series inductance due to the actual probe leads, not to mention the ground lead inductance. The isn't as simple as just terminating with the line impedance at either end, look at my earlier post that shows the simulation which attempts to get a waveform at the scope connector that "looks" like the waveform tautech provided from the OEM LA. Figuring that "IF" the waveforms look similar, then the LA networks should be similar and the performance similar, I know at lot of "IFs"

For these reasons when we did our PCB version we included the addition components to allow better control of the impedances "seen" at the input and output of the transmission line, wether it's a micro-coax, twisted pair, or simple ribbon cable.

Still waiting on the Dupont crimp tool, and sidetracked on another involved project (64 channel MMW phased array controller based on a new integrated technology voltage controlled transmission line for the delay elements), so hope to get back to this LA project soon.

Disregard the 0.1uF cap values shown in the schematic, obviously these should be in the few pF range!!

Best,

[Bad_Driver]

I checked different old monitor cables as well. Old VGA cables have 3 thin coax with 75 ohms (measured) inside and other thin twisted cables.

But I will stay with twisted pair cables from DVI cables as suggested by Thomas. My interests are more on the "DC side" of digital electronics.
But it would be interesting to see if there are real differences with different cables and terminations up to 500 MHz. May be someone
tries it.

Unfortunately my 3D printer seems to suffer from a defective main board and needs much more efforts than I can spend these days.
So I cannot print the shells for the PCBs.  Hope to overcome this issue and be able to finalize the logic probe set. The tips arrived from Aliexpress.

[Old Printer]

Wish there was a version for the 1104x-E 
Don't really want to spend the extra $900 to upgrade to the 1204 plus, though that is a beautiful screen.

[oz2cpu]

to old printer : Siglent SDS1104X-E  dont have Logic Analyzer

---

 if we where playing with analog signals, cross talk is much more visible, and important to avoid.
but a logic analyzer is DIGITAL, and it is alot more imune,
I tried many different signals at the same time, from 10 to 500MHz at the fastest rise times my generators can create,
and I am not able to detect any cross talk.
so it is really noth worth the trouble and hard work, to use coax, it is a nightmare to solder, and much more stiff..
just take what ever thinn wires you got, and twist them.. done deal..
IMPORTANT : cut all wires to exactly the SAME length, look at the PCB's i made, all tracks are exactly the same length, and as short as possible,
and spaced as much as possible, and made so their individual capacity, inductance, cross talk, is as little as possible, and as even channel to channel as possible,
when running tests at 500MHz with 1nS rise time, it is barely visible the different response i get on the scope,
and some of it could just as well be inside the scope, it is that little.

[Old Printer]

to old printer : Siglent SDS1104X-E  dont have Logic Analyzer

It is supposed to have MSO with a $109 firmware option, which I believe is hackable, and a $329 16 Channel Logic Probe set of leads. Maybe it does not have the active components built into the scope as the 1204+ does??

[oz2cpu]

I just checked its specs, cant even find the LA connector, on that scope

[2N3055]

I just checked its specs, cant even find the LA connector, on that scope

There is S_bus connector next to USB.. It uses external device that does acquisition, that is not passive and you have to buy it... It works but is not as powerful as 2000X+ with fully integrated MSO.
If MSO is really needed, instead of buying SLA1016 for 350 €, I would put that money forward to upgrade to SDS2000X+. And if you sell SDS1104X-E  you recoup some money too.
SDS2000X+ is whole different level..... If you can  afford it, that is clear winner...

[mawyatt]

Recall somewhere that the LA for the lower level Siglent scopes had significant active circuitry, thus more difficult to DIY implement.

Agree with 2N3055, with the Siglent SDS2000X+ and with the Thomas DIY LA (completely passive) you've got a really good setup. Don't worry too much about the twisted pair or coax for the LA, both should perform well, even the Ribbon Cable we used seems to work well at lower speeds. Of course if you are trying to squeeze the best overall performance for the LA, then not only the cable type but the impedance networks in the LA base and POD must be tuned, but this is an ongoing effort we hope to get back on soon 

Just used the SDS2102X+ to show results from a mathematical solution of a coupling network (don't want to clutter this thread with details unless others are interested), what an absolute jewel of an instrument IMO. Being an old retired EE that has used about every analog scope Tek ever made, I was naive about the capabilities of these new MSOs. Since getting the Siglent, the pair of Tek 2465s haven't been used much, the Siglent is that good and right away became a very useful instrument

Best,

[Johnny B Good]

 I'm quite impressed with mine but I do have a couple of minor criticisms. The most significant being the 46 seconds boot up delay versus the 16 seconds of the SDS1202X-E and the not quite so significant yet much higher than expected increased power consumption (54W versus the 22W of the 1202).

 In view of the almost 2 1/2 times greater energy consumption, suggesting the use of a more power hungry faster processor, that significantly protracted boot up time is a rather surprising shortcoming. I can only assume the extra channels and larger feature set have added to the initialisation burden with additional time constraints that no amount of extra CPU grunt can mitigate - the price of progress in this case, perhaps? 

 I hope this isn't the start of a trend leading us back to the days of those Tektronix 500W space heaters so cunningly disguised as test and measurement kit labelled "545A Oscilloscope". 

[oz2cpu]

if boot up time is an issue Johnny,
try this : Tenma 72-8225a 50mhz 2 Channel Digital Oscilloscope With 500ms/s Sampling Rate

it takes 4 sec, from power on, THEN it is fully ready to rock :-)
I have not seen anything beat this.
Sold it, got a Rigol,
sold the rigol, got a Siglent.
Every time I got alot more bootup time.
but really not an issue for me, I used to work with R&S RTO scope, it is a few mins of bootup and a loud storm of fan noise

[2N3055]

I'm quite impressed with mine but I do have a couple of minor criticisms. The most significant being the 46 seconds boot up delay versus the 16 seconds of the SDS1202X-E and the not quite so significant yet much higher than expected increased power consumption (54W versus the 22W of the 1202).

 In view of the almost 2 1/2 times greater energy consumption, suggesting the use of a more power hungry faster processor, that significantly protracted boot up time is a rather surprising shortcoming. I can only assume the extra channels and larger feature set have added to the initialisation burden with additional time constraints that no amount of extra CPU grunt can mitigate - the price of progress in this case, perhaps? 

 I hope this isn't the start of a trend leading us back to the days of those Tektronix 500W space heaters so cunningly disguised as test and measurement kit labelled "545A Oscilloscope". 

Keysight MSOX-3104T boots 1 minute, 45 seconds.. That's 105 seconds...
 Enjoy your very fast booting scope...

[Johnny B Good]

 @oz2cpu

 Thanks for offering that perspective. I guess it's normal to not only expect more performance and features for the extra money but also more boot time and power consumption too! The thing was, I just wasn't expecting to get quite so much of either.

 Intrigued, I googled "Tenma 72-8225a 50MHz" only to find SFA information in the two page 'datasheet' provided by Farnell for their UNI-T rebrand which they're now selling the 1Gsps version for a mere £197.20 (VAT inclusive price) which is half the typical Ebay sellers' price point (the cheapest being £320). It's unusual to say the least, to find Farnell undercutting competing sellers by any amount let alone by more than 50%!

 If anyone's in the market for an 'entry level 'scope, they certainly won't be buying a Tenma 72-8225a from any of these sellers

https://www.ebay.co.uk/sch/i.html?_from=R40&_trksid=p2334524.m570.l1313&_nkw=Tenma+72-8225a+50MHz&_sacat=0&LH_TitleDesc=0&_osacat=0&_odkw=Tenma+72-8225a+2nd+hand

 Nor from this one

https://uk.farnell.com/tenma/72-8225a/oscilloscope-2-ch-50mhz-500msps/dp/2499522?mckv=soDoPBV12_dc|pcrid||plid||kword||match|e|slid||product|2499522|pgrid|1357897483847209|ptaid|pla-4588468182313071|&CMP=KNC-GUK-GEN-SHOPPING-SMEC-WHOOPS-Test725-minROAS-Step1&gross_price=true&msclkid=a71687df1b5f1abf0db7e775b3d6aa13

There's some very peculiar price variations being applied to this Tenma 72-8225A 'scope.

 I can see the appeal of a 'scope priced at just £197 to the cash strapped hobbyist whose needs are rather modest but I can't figure out the appeal when they're being priced at £334.57 and higher. Surely, anyone checking out this budget end of the 'scope market will have already seen the better alternatives from Rigol and Siglent in their searches? I mean  Who would be so stupid as to pay those prices for a UNI-T 'scope sullied by the Farnell branding?

[EDIT]

 For those whose budgets just won't stretch to Rigol or Siglent kit, there's always the  Hantek DSO2D10 available from BangGood priced at just £164.95 (plus £9.24 shipping fee to the UK from their CN warehouse). Cheaper again with 1GSa/s 100MHz BW plus a built in single channel AWG (25MHz max sine) with nicer looking on screen fonts.

https://www.banggood.com/Hantek-DSO2D10-Digital-Oscilloscope-2CH+1CH-Digital-Storage-1GS-or-s-Sampling-Rate-100MHz-Bandwidth-Dual-Channel-Economical-Oscilloscope-with-Signal-Source(AWG)-p-1765904.html?cur_warehouse=CN&rmmds=category

 I spotted this in one of today's BangGood junk mails and decided, in view of my contributions here, to take a closer look. It's actually quite well specced for the money (it even includes an extra 9 to 10 second's worth of boot up time  ). Indeed, if it had been available at that price two and a half years ago when I'd been looking to upgrade a 5MHz BW boat anchor that was already ancient when I'd bought  it some 40 years ago, I may well have purchased that instead as my very first modern day DSO.

 Trying to track down any meaningful reviews on this Hantek led me to a how to hack it to 200MHz BW youtube video with a link to a 125 page EEVBlog thread originated way back in October 2010 active right up to the 11th of this month!

https://www.eevblog.com/forum/testgear/hantek-tekway-dso-hack-get-200mhz-bw-for-free/msg21170/#msg21170

 for anyone curious enough to take a look.

 Even at the reduced price, I can't really see Farnell selling many (if any) of these rebranded UNI-T DSOs. 

[Johnny B Good]

I'm quite impressed with mine but I do have a couple of minor criticisms. The most significant being the 46 seconds boot up delay versus the 16 seconds of the SDS1202X-E and the not quite so significant yet much higher than expected increased power consumption (54W versus the 22W of the 1202).

 In view of the almost 2 1/2 times greater energy consumption, suggesting the use of a more power hungry faster processor, that significantly protracted boot up time is a rather surprising shortcoming. I can only assume the extra channels and larger feature set have added to the initialisation burden with additional time constraints that no amount of extra CPU grunt can mitigate - the price of progress in this case, perhaps? 

 I hope this isn't the start of a trend leading us back to the days of those Tektronix 500W space heaters so cunningly disguised as test and measurement kit labelled "545A Oscilloscope". 

Keysight MSOX-3104T boots 1 minute, 45 seconds.. That's 105 seconds...
 Enjoy your very fast booting scope...

 Oh, don't worry about that. Now, thanks to both oz2cpu's and your contributions, I surely will! 

[mawyatt]

Enjoying these SDS2XXX+ scopes indeed!!

Just finished using the superb Bode Plot feature to help evaluate a few HV Op Amps, then leveraging of Thomas's excellent DIY LA Probe to trace down a bug in the Analog Devices software/DAC hardware test PCB.

For the bug tracing this required finishing up the version of the DIY LA Probe that utilizes a 3M controlled impedance twisted pair cable with connectors since using standard ribbon cable could create false "glitches" with the SCI signals and wanted to make sure we were tracing the real bug/glitch rather than a cable induced glitch. This LA Probe allowed us to find that the AD software wasn't issuing a correct LDAC command and why the DAC output voltage wasn't being updated.


Best,

[oz2cpu]

nice with a little bit LA user-case-stories

please people, do tell when you use LA, and what it did for your project
post pictures, and screen shoots :-)
we love to hear about when the Logic Analyzer feature is so fantastic.

[mawyatt]

Ok, here's a few images of the setup and the LA Probe using the twisted pair cables with connectors on each end. The component values for the POD are input R of 250 ohms followed by 90.9K in parallel with 8.2pF, the BASE is 360 ohms series R to scope. The shunt elements in the base are not installed and these are for "tuning" the response for maximum BW and good pulse shape, but this must wait until time permits.

The cases are 3D printed but still learning this process, so not as nice as could be

Anyway, works nicely with our "enhanced" SDS2102X+ and really like the display and SPI serial bus decoding. Agree with Rob at tautech, having a few more analog traces along with the 16 bit digital traces of the LA should prove valuable when we get to the multiple DAC outputs of the present project.

This is my first use of a LA and must say hats off to Thomas and Siglent for making this experience worthwhile and useful

Best,

[Slartibartfast]

However, we can verify that Thomas (oz2cpu) LA Probe works well with standard 10 line ribbon cable (8 active, 2 ground), the twisted pair cable we have is a little too wide so used ribbon cable instead. Don't have a high speed pulse generator, but did verify that using a sine wave input from a AWG the Probe works to ~100MHz with ribbon. You do "see" a small amount of crosstalk, but that's expected, with twisted pair the crosstalk should be eliminated.

I wonder ...

At RF, inductive, capacitive and even radiative coupling are so much worse than at AF (audio frequency), that RF guys frequently neglect thinking about galvanic coupling. Usually that can be justified if a massive, low-impedance ground plane can be used. Here, we do not have such a ground plane. In fact, the two concepts discussed in this thread have TWO separate ground planes (one in the pod, one in the scope adapter), connected by a set of ground lines. I'm not sure whether that concept is a smart idea, I think a significant part of the crosstalk may be due to galvanic coupling.

What happens if a logic signal edge travels along signal line, say, #3? Some current will flow in the line, and some return current will flow in the ground line. Which ground line? After all, all ground lines of a pod connect the same two ground planes. Well, the ground line that is associated with the signal line, i.e. ground #3, will carry the majority. The reason is that this ground line out of the eight forms the lowest inductance loop with the signal line. But in the same way as a 10k resistor parallel to a 1k resistor also carries a smaller part of the current, the other ground lines will also carry a part of the return current that ought to travel via ground #3. I'd expect that part of the return current to cause crosstalk to the signals on lines #2 and #4, and, to a lesser degree, to the other signals.

For this reason I think it may be smarter to keep the grounds of the various signals separate inside the pod. IMHO this would reduce the crosstalk that you measured. The final purpose of a logic analyser however would in most cases have the grounds connected inside the DUT anyway, so I'm not sure how much difference it makes in terms of the real-world application of the device.

Cheers  Peter

[Slartibartfast]

Mike,

I really like your concept with the detachable pods. I'd envision that I'd more often use the LA with the less than 8, rather than more, channels. Having only one cable lying around would be useful.

Maybe I missed it, but did you post your design files?

Cheers  Peter

[ElectronicsHobbyist]

Hi Peter

All design files are on thingiverse (See first post on this topic).
Im about to order them right now by the way. Thanks very much to oz2cpu and all the other developers for developing and publishing this great piece of equipment.

[mawyatt]

However, we can verify that Thomas (oz2cpu) LA Probe works well with standard 10 line ribbon cable (8 active, 2 ground), the twisted pair cable we have is a little too wide so used ribbon cable instead. Don't have a high speed pulse generator, but did verify that using a sine wave input from a AWG the Probe works to ~100MHz with ribbon. You do "see" a small amount of crosstalk, but that's expected, with twisted pair the crosstalk should be eliminated.

I wonder ...

At RF, inductive, capacitive and even radiative coupling are so much worse than at AF (audio frequency), that RF guys frequently neglect thinking about galvanic coupling. Usually that can be justified if a massive, low-impedance ground plane can be used. Here, we do not have such a ground plane. In fact, the two concepts discussed in this thread have TWO separate ground planes (one in the pod, one in the scope adapter), connected by a set of ground lines. I'm not sure whether that concept is a smart idea, I think a significant part of the crosstalk may be due to galvanic coupling.

What happens if a logic signal edge travels along signal line, say, #3? Some current will flow in the line, and some return current will flow in the ground line. Which ground line? After all, all ground lines of a pod connect the same two ground planes. Well, the ground line that is associated with the signal line, i.e. ground #3, will carry the majority. The reason is that this ground line out of the eight forms the lowest inductance loop with the signal line. But in the same way as a 10k resistor parallel to a 1k resistor also carries a smaller part of the current, the other ground lines will also carry a part of the return current that ought to travel via ground #3. I'd expect that part of the return current to cause crosstalk to the signals on lines #2 and #4, and, to a lesser degree, to the other signals.

For this reason I think it may be smarter to keep the grounds of the various signals separate inside the pod. IMHO this would reduce the crosstalk that you measured. The final purpose of a logic analyser however would in most cases have the grounds connected inside the DUT anyway, so I'm not sure how much difference it makes in terms of the real-world application of the device.

Cheers  Peter

Don't think this is a galvanic coupling issue, it's simply signal edge coupling to adjacent lines due to dynamic fields. With twisted pair or coaxial lines there is little EM field outside the pair or coaxial line, and thus little coupling to adjacent lines. A few simple tests proved this once the twisted pair LA was assembled and tested, no coupling whatsoever to any lines under any signal conditions we could generate.

We are using this twisted pair LA now without any issues, coupling or otherwise. It works beautifully with either the SDS2102X Plus or SDS2104X Plus (both enhanced) without issue

Best,   

[mawyatt]

Mike,

I really like your concept with the detachable pods. I'd envision that I'd more often use the LA with the less than 8, rather than more, channels. Having only one cable lying around would be useful.

Maybe I missed it, but did you post your design files?

Cheers  Peter

I didn't't post my design files, they are different than Thomas's files. I use the single 8 bit input mostly, in fact have yet to find a need for the full 16 bits use, and could even use the single bit lines now since I'm sensing SPI lines.

Best,

[Slartibartfast]

I use the single 8 bit input mostly, in fact have yet to find a need for the full 16 bits use, and could even use the single bit lines now since I'm sensing SPI lines.

That is exactly what I anticipate for my usage scenarios too, hence my preference for detachable pods and wiring.

So I'll do my own design then. Should not be much work given all the information on the circuitry you have provided in this thread.

You have correctly pointed out that oz2cpu's in line resistors at the base do not terminate, but it seems in your design you also only use in-line resistors, instead of parallel-connected terminators. Is that work left for the future, or is there some background to it that you did not explain in the thread?

[mawyatt]

I use the single 8 bit input mostly, in fact have yet to find a need for the full 16 bits use, and could even use the single bit lines now since I'm sensing SPI lines.

That is exactly what I anticipate for my usage scenarios too, hence my preference for detachable pods and wiring.

So I'll do my own design then. Should not be much work given all the information on the circuitry you have provided in this thread.

You have correctly pointed out that oz2cpu's in line resistors at the base do not terminate, but it seems in your design you also only use in-line resistors, instead of parallel-connected terminators. Is that work left for the future, or is there some background to it that you did not explain in the thread?

I did some simulations of what I thought the scope input looked like, and was able to get a close pulse response to what Rob at tautech had shown (measured, see earlier in this thread). First off the twisted pair is not terminated with the characteristic impedance (100~130 ohms depending on the cable) on either end, this would load the input probe too much and attenuate the signal too much at the scope end. The cable is AC terminated with an RC network on each end that allows a reasonable input impedance as "seen" for the device being probed and doesn't attenuate the signal too much for the scope to sense. The network I did allows this with select Rs and Cs. However, I have not had time to create the optimum network RC values just yet, will do so later when time allows, so for the beginning just included the series resistors and series capacitor.

Here's what the schematic and PCBs look like. I got 2 types of twisted cable off eBay for ~$25 each, the one I've used is like the 3M type mentioned in the thread, the other is a larger cable but should also work. Also have a few PCBs somewhere, but really don't have the time now to pull all this together (in middle of a major project which is benefiting from this LA), later in a couple months. PM if you want more details or files if I can get them easily.

Best,

[mawyatt]

Few more.

Best,

[Slartibartfast]

here you go, i think TK was the one to first provide the pinouts, he shared this file attached,

There is something wrong here. TK seems to have messed up the side designations.

PCIexpress standard documents state the "lower side" of the board (i.e. "solder side") is "Side A", while the  "upper side" ("components side") is "Side B". This coincides with the orientations of the PCBA sides when looking down the PCIe card onto the PCIe socket, and placing it such that the 11-pin section is at the left, with pin counting from left to right (in a PC, this amounts to placing the I/O shields to the left). (edit: used to be with PCI but incorrect for PCIe)

TK has called the lower side "Side B" and the upper side "Side A", in contradiction to the standard. Depending on whether the table was meant to give the layout looking into the socket, or onto the edge connector, either could be right. So, in the two header lines in the pin table posted by TK, which is the correct line? The one denoting A vs. B, or the one lower vs. upper?

Since we're dealing with a scope that clearly defines directions up and down I suspect I can trust the "Upper" vs. "Lower" designation, and "Side A" vs. "Side B" are chosen arbitrarily (opposite to standard). Can somebody confirm, or state what is correct?

Edit: Just realised the fact that in a typical tower case PC the PCBA is mounted upside down (component side pointing down) may be the source of the confusion. If that is true then indeed TK assigned A and B correctly, and with "upper" and "lower" he just referred to the sides as referring to the scope's "up" and "down", different from the PCIe standard which has the component (upper) side down, and vice versa.

https://web.archive.org/web/20111102042843/http://www.adexelec.com/faq.htm#pcikeys

[oz2cpu]

if you look at the pictures of the pcb layouts in post 1
you will see what is what,
also the pcb is impossible to flip in the 3D printed case, and the edge connector and case is impossible to stick into the scope wrong.
you are welcome to reinvent it all, once again,
but you can also just download the free available ordering zip, send it to JLC or similar place
3D print the shells, and be done in a week,
it is a well tested design, we are many users now on this design.
here is a picture from last week, when i designed a PID system for a robot motor controller

[AlexDavidson]

Thanks to the great work by oz2cpu and the boards he sent me, I’m now able to use the digital channels on my SDS2000X+. I had no problems printing the cases and assembling everything, and it all seems to work as intended. A note to others using this solution: the wires used for cabling shouldn’t be more than 0.75mm diameter otherwise you will have trouble soldering to the boards and fitting into the cases. I used twisted pairs removed from HDMI cable as suggested earlier in this thread.

The main reason I wanted to enable the digital channels was to assist in debugging communication problems in a project with 6 daisy-chained SPI devices (AS5048A encoders). Using the LA probe I was able to connect 4 digital channels to the master SPI, freeing up the analog channels to look for noise etc along the chain & power supply rails. I used both pods so I could set 2 different thresholds, because some of the signals were 5v & others 3v3. At one point I also connected digital channels to the MISO/MOSI interconnections along the daisy chain to check that data was being shifted along correctly, but this is not shown in the capture below.

For those interested, the trigger for the capture below was MISO bit 14 set, which happens to be the AS5048A error flag bit. Decoding was set to use clock timeout because CS only changes every 6 packets. S1 & S2 are both decoding the same data - one is set to hex display, the other to binary to make it easy to spot bit patterns. The analog channels were connected to CS & CLK as a cross-check for glitches, and C3 was connected to an MCU output pin used for debugging.

Following the trigger, which in this case came from the 4th encoder in the chain, code in the project sends a UDP packet to a host PC, which is why SPI data stream pauses for about 200 us before transmitting the 5th and 6th packets. Next the code sends 0x4001 six times to clear the error registers in the AS5048As, before resuming sending 0xFFFF, which is the read angle command.

It took a while, but I’m happy to report that I did eventually sort out the comms problems with all those extra channels to play with. (Those AS5048A encoders seem very fussy when it comes to output loading, and very susceptible to noise on the clock, which is a bit annoying since they are likely to be used in a noisy environment, e.g. with stepper motors as in my case.)

I did however notice a few issues with the Siglent along the way, mainly to do with SPI triggering and decoding, which didn’t always seem consistent. After changing something, say the SPI trigger conditions or channel mapping, I would sometimes have to play around with thresholds or cycle the SPI settings to get it working correctly. Sometimes the decoding was clearly incorrect (not just the last bit issue mentioned in the bug thread), and sometimes it would trigger on the incorrectly decoded data; other times not. Part of this might have been due to the rats nest of connections to the project or me, however I didn’t have the same issues on my Keysight MSOX3000 series scope when I tried connecting it in parallel with the Siglent (making an even bigger rat’s nest).

Yes it would be nice if the digital channels didn’t have these issues, but we can’t ignore that the Siglent is excellent value for money, even more so with the DIY LA probe.

[oz2cpu]

thanks for getting back to us all Alex,
it is super nice to hear how real work experience turn out to be.
we are a few who have seen the data trig issues, i2c, serial and spi, all is with a few minor bugs in the scope,
if you look for the bug found and suggestion thread, siglent monitor it,
I hope they will fix the reported issues soon, and release a new fw.

[TheDefpom]

Thank you all for the work on this DIY LA module.

I have almost finished building one, I had to make some changes to the scope connector shells to allow more room for wiring inside it, I am using coaxial ribbon cables salvaged from a Tektronix LA pod.

I put my version of the scope connector shells up on my thingiverse here: https://www.thingiverse.com/thing:4964027

I have been recording footage to do a video about it for my youtube channel, which I expect to publish either this week or next week.

I haven't actually tried using it yet, once I get the shells all finished and it is built, then I will do some testing of it with all 16 channels, but the electrical tests I have done so far on the cables all look good so I don't know why it wouldn't work.

[oz2cpu]

looks great, thanks for sharing.
I add your thingiverse link, to post 1
so we have it all collected one place.

[oz2cpu]

my first audio dubbed video, darn that took forever to make :-)

i got my hands on a Siglent LA SPL2016 probe set, and could finally test it side by side with my own DIY
https://youtu.be/paKK0c-4pgw

[TheDefpom]

Here is my logic probe build video:

[FrancisM]

Hello,

I wanted to test my LA at a higher frequency than those I use it most the time. 100MHz was the target, it's the fastest I can reach with the trough hole PICs at my disposal. I mounted a dsPic33EP in a dead bug style and overclocked it at 100MIPS, way over the 70MIPS given in the datasheet. I never tried it before but it works, at the expense of a jitter of around 900ps.

I used some cheap SDK08 grabbers I got recently. Looking nice but one has been badly mounted and is only usable on big pins, not smd. The hooks don't retract enough. Another one went electrically open during testing while ok mechanically. You get what you pay for.

I first tested at 50MIPS with different patterns for a maximal loading on all the lines. It was all good.
At 100MIPS, only the single walking bit was fine. The scope didn't even trigger on the other patterns. A single trig revealed a lot of crosstalk everywhere. The cure was to add a third ground line between each POD and the DUT.

I will probably never use the analyser at this speed, it's just good to know it behaves well.

Francis

[oz2cpu]

wow FrancisM, thanks for the curves,
but dont you think the jitter is due to your software ?
and the way you trig ?
is it assembly ?
any conditional jumps ?
counters ?
it looks clearly like your code is not taking exactly the same time, each time thru
even a counter and a compare, will do that.

[FrancisM]

Hi oz2cpu,

The jitter comes clearly from the PIC. It's for a reason Microchip gives an upper limit of 70MIPS for this chip. At this frequency, the output pulses are clean. At 74MIPS, the jitter starts to appear and the higher I go, the more I get.
I tried to clock the PIC with the AWG of the scope. This setup allows a max 25MIPS without using the PLL and it gives a perfect result. Single rising and falling edge on all digital lines. As soon as I engage the PLL and rise it's frequency, things worsen. My PIC is the limit and I knew it from the start. I have actually no other gear to provide 10ns pulses or less on 16 output lines.

The program is assembler and it's my first one on dsPIC. I made it to have no dead time between pulses, linear programing, no interrupts, just one inconditional branch to loop and this one takes three cycles, incredible.

The most important thing I learned is to have enough ground paths on each POD.
I'm pleased with the result and can be confident with everything I will do with this gear.
Thanks for the good job Thomas.

Francis

[oz2cpu]

thanks for the uptate,
yes clearly a way to go with assembler,
looks like your pulses are very well designed,
it would be impossible to make them this clean with C
so what you say is : the jitter come from the overclocking = instabilities revealed just before total fail, near the max point.
very interesting observation, the methode is easy to recreate and idea can be reused to find the near max
of other devices.

[FrancisM]

I tried to test how far the PIC could go without any output loading. It stopped working at 113MIPS with DC on the output I was monitoring.

[Johnny B Good]

Season's greetings to one and all.

 I've been following this thread from its beginning. I've not as yet committed to building this rather fine DIY version of the siglent spl2016 until I came across this eBay seller, atomicfrenzy, selling the following diy kit here:

https://www.ebay.co.uk/itm/224681365190

 Being able to buy all the required parts (but with only 8 test hooks) in one go makes the project so much easier for me to complete than if I'd had to order them separately. I'd have bought the official logic probe kit but the idea of spending as much as the current price of my three year old SDS1202X-E on what is essentially a bunch of cleverly wired connectors with a handful of smd passive components seems somewhat obscene to my mind, hence my interest in going the diy route, even if I'm cheating a little.

 I messaged the seller, originally just to ask if he could supply an additional pack of test hooks, but noticed cheaper item and shipping charges pricing at the top of the message form so I have asked him to clarify the pricing details before I place my order.

 I'll let you know the resulting answer all in good time.

[oz2cpu]

hi john, it surely looks like 99% "my" pcb designs, and 99% my 3D case designs
and like i allready said : the design files are all free to make, use,
and to sell at part cost, what this seller does is exactly that, so far i am happy.

however i am a little bit nervious about the flat cable implementation,
all the tests we have done, was with carefully twisted pairs (gnd and each signal)
yes it is a hazzle to make,

if you dont expect to use it, at its maxium potential speed,
it might not be a practical issue for you.

ONE EXTRA IMPORTANT NOTE : the main pcb MUST be 4 layers !!
the ebay design looks like it is modified to be 2 layers !! the layer identifier is modified so it is hidden, to see the two inner layer numbers !!
you need to have this confirmed before purchase !!
this is a rist that happens, when some one "copy" and modify designs..

[Johnny B Good]

 I'd already placed the order by the time I was alerted to your message. I have just messaged atomicfrenzy asking him to confirm that the main PCB ('scope connector) is actually a four layer board.

 I'm expecting a fairly swift response since he'd replied within 12 hours of my initial query over pricing and an additional set of test hooks.

 I'll post the result of that communication asap.

 Regarding the use of flat ribbon cable, I was already aware of the problem (from the discussions in this thread). I took the view that this was an upgrade I could apply as soon as I could source suitable micro-coax or twisted pair ribbon cable.

 He'd made it quite clear in the description that the kit had been designed for use with such cable and posted test results with the supplied 24 inch lengths of Belden ribbon cable so I was happy enough with the essential parts of the kit being supplied, based on the assumption that these were in fact based on your board designs as he freely admitted in his first reply.

 Hopefully, he can confirm the use of a 4 layer board for the 'scope connector end and all will be fine, otherwise I will be cancelling the order on the basis that it is 'not as described'.

[oz2cpu]

SUPER, if the main pcb is 4 layers, the copy design is done in error, and should be corrected, the layer identifier MUST reveal the inner layers
if it is 2 layers, you be better of cancel the order, and order the pcb from jlc
the correct files, that works are free (why the heck edit them the first place ??

[Johnny B Good]

 I've just edited my previous reply, BTW.

Regarding his 'editing', this might simply have been to enable 'panelising' of that board to minimise costs (a close look reveals the 'mouse bites' on the main board which he had pointed out to me in his initial response). Hopefully, this is the only reason why he edited the original design. I guess I'll find out one way or another soon enough.

[oz2cpu]

milling combined with Vcut, no big deal, also looks like the connector edge is not sanded, in my STL file set, you find the sander tool
with this one you can sand at perfect angle and make the line straight, it is nearly impossible to do correctly without,
I tried, it looks bad

[Johnny B Good]

 He's even included the sanding tool (inluding a sheet of glass/sanding paper) which bodes well for the expected reply (fingers crossed) - see attached image.

[oz2cpu]

super, happy sanding, and i really hope it is 4 layers
just a bit sad the layer identifier is performed wrong, so you cant see thru
I design pcb's for a living, so I am a bit crasy when it come to the layer identifiers, you know it is a nice way to confirm you got
somewhat close to what you ordered :-)

[Johnny B Good]

 Unfortunately, the answer I got was in the negative. It is, as you suspected, only a two layer board. He's claiming that with the board only being an inch long, the absence of the additional groundplanes should only matter if I were planning on analysing 4GHz clocked signals.

 How small an issue it might be up to a 500MSa/s and a 3.3ns minimum pulse width limit as he claims is a bit too much of an unknown for me to answer so I'm asking you whether I should place any credence in his claim that this would be the case. I suspect your answer will be "No" and "just cancel the order."

 I could PM copies of the email exchanges for you to peruse privately rather than here in a public forum if you like but, in short, his initial claim in the first email that

 "This is the same thing you could make if you download the files from that topic."

 (referring to this topic thread) has proved by his own admission in his 2nd reply, that he'd modified the board design beyond merely allowing it to be panelised by making it a two layer only PCB, thus breaking the terms of use of the licence you'd granted.

 The thing is, despite this, it's an otherwise convenient way to acquire the parts for this project, even if it means ordering a main PCB from JLC. The unknown here being the additional cost this step would involve.

 I'm probably better off cancelling the deal via the eBay resolution service since by his own admission, it hadn't been "as described".

[rogersstuart]

Johnny, you're stressing a lot over a $20 kit and a 500 Ms/s logic analyzer. 250 MHz would be the Nyquist frequency. If this was a normal scope channel then you would have two points for for your sin(x)/x. 1/5 of that is equivalent to 100 MHz which is a good upper limit for signals that you might use with this. There may be a bandwidth spec somewhere. I'm not sure what it is. I can tell you that even the MSO5000 with twice the sample rate doesn't do well with logic signals of that frequency. And with your clocks not being synchronized, is that enough to result in what you're seeing not jittering around? I'm not an expert on how logic analyzers are designed. Maybe I'm wrong about why but it fits what I've seen. 25 MHz seems to be a good limit based on my testing. If you want the ground planes then you should also hunt down some nice 120 ohm coax to go with it which isn't easy or cheap. Also, these accusations aren't cool bro. I didn't say that it's 4 layers or lie about anything on eBay. I stumbled across this just like you and decided to sell the extra parts I had. I have to supply you with $5 of little probe clips, hand assembled boards (placing those passives hurts my back) baked in a modified toaster oven in my kitchen, cleaning in an ultrasonic cleaner, 3D printed parts that I blow hot air on to clean up wisps, sandpaper, ribbon cable, packaging, having a car, rent, and dealing with all the other stuff like responding to people (while I'm playing the new Final Fantasy video game) and testing things. I'm sure that's why the creator isn't selling them anymore. It's not worth the hassle. But I kind of like it. Someone from Japan ordered one yesterday which is cool. And I've sent one to Australia. So far, no complaints and I think that's 6 sold so far.

edit: I have been thinking about this. There isn't a lot said in the specification about the limitations of the logic analyzer. I was bothered by the fact that the signal jitters around a bit at higher frequency but I think it makes sense. If you have a 50 MHz signal, that's a 20 ns period. For a square wave at 50% duty cycle, half of that time will be high or low. One of those state will be around for 10 ns. With a 500 Ms/s sample rate we get a sample every 2ns. So, during this short 10ns window you would have only 5 samples. If things aren't perfectly aligned you would sometimes see quite a bit of jittering around.

[oz2cpu]

> I'm probably better off cancelling the deal via the eBay resolution service since by his own admission, it hadn't been "as described".

YES you are, Better just order the propper 4 layer pcb from jlc
order 10 set of each type, and offer to sell the propper design to others, feel free to use this page,
and please twist the cables as explained in the thread

what makes me sad and confused is : why would someone take this design,
modify it to the worse, forget to place link refferance to the design origin as required,
and with out change explain, sell it as the original, he even write 4, on the bottom layer, while the correct number should have been 2,
this is only a cover up stunt, i am not so happy with this.
it is my good name and reputation that is poluted,
when the end user get stuff that is not as expected..

[Johnny B Good]

@rogersstuart

 I gather from this that you are the eponymous atomicfrenzy I've been exchanging messages with via the user hostile evilBay messaging system (which seems to have sent my last 'thank you' reply to the bit bucket).

 That being the case, I'll repeat the gist of that message here, taking the opportunity to thank you for swiftly cancelling the purchase and refunding my Paypal account. I have no reason to bear you any ill will since you'd resolved our disagreement in a timely and honourable fashion.

 I think the only mistake you'd made was in trying to cut costs on the main PCB in order to hold the end price down. Here, I think you'd made a rod for your own back when you consider that passing on the higher cost to the end customer is allowed by the licensing terms provided by oz2cpu and the kit price was only two thirds that of the shipping costs alone to begin with (to Europe and the UK at least) where the resulting 50 dollar total still only represents a mere 11.6% of the full £360 asking price (one whole SDS1202X-E's worth in fact!) of the Siglent kit here in the UK.

 As I also mentioned in that now missing reply, should you ever decide to replace the two layer board with the four layer one as per oz2cpu's original design, I'd be only too happy to buy from you again despite the fact that it'll likely add another 5 dollars or so to the kit price.

[tautech]

@Johnny B Good

I was pondering this for a bit and decided to take a look at the original files. I think I know where the confusion came from.

In his (oz2cpu's) original design there was no ground fill on the top and bottom. If this had been made by simply omitting the inner layer gerber files then it would have not worked. When I edited the files I added a ground pour to the top and bottom to add a continuous ground throughout. If this was a microwave circuit then it would have not been appropriate to do so without net via shielding and recalculating the width of the traces. But for the frequencies involved I feel like it was appropriate and the coupling between the sides is insignificant compared to the input impedance. The only concern you should have is about the ribbon cable. But I do mention in the listing that it was designed for 120 ohm cable and that I did not include it, so I feel like I was being fair by mentioning that.

I don't want to get into an argument about international law here. Suffice it to say, I am well within my rights to reproduce a non-patented hardware design or take inspiration from one. Your concern should only be if I am attempting to defraud you, which I'm not. I have tested this and it works. That's all I can say to convince you. Really, all you had to do was test it and talk to me. I have had to work with people who have burned PCBs with a torch and want a refund. If you buy it and it doesn't work then deal with me that way. Starting with accusations is not productive between a buyer and a seller.

You're advertising: Siglent SPL2016 Compatible DIY Logic Probe
That it certainly isn't ! ! !

While it may fit a SDS2000X+ DSO and behave similar to SPL2016 it can in no way challenge the original performance.
Best you have a squiz at the specs here:
https://siglentna.com/wp-content/uploads/2021/05/Digital-Probe-Datasheet-V20E201912.pdf

FYI, original SPL2016 are supplied with 20 quality grabbers and not some POS grabber that falls of if you sneeze on it.
Offering a cheap low level substitute DIY MSO probe that fits a SDS2000X Plus would be well advised rather than mention of SPL2016.

[2N3055]

@Johnny B Good

I was pondering this for a bit and decided to take a look at the original files. I think I know where the confusion came from.

In his (oz2cpu's) original design there was no ground fill on the top and bottom. If this had been made by simply omitting the inner layer gerber files then it would have not worked. When I edited the files I added a ground pour to the top and bottom to add a continuous ground throughout. If this was a microwave circuit then it would have not been appropriate to do so without net via shielding and recalculating the width of the traces. But for the frequencies involved I feel like it was appropriate and the coupling between the sides is insignificant compared to the input impedance. The only concern you should have is about the ribbon cable. But I do mention in the listing that it was designed for 120 ohm cable and that I did not include it, so I feel like I was being fair by mentioning that.

I don't want to get into an argument about international law here. Suffice it to say, I am well within my rights to reproduce a non-patented hardware design or take inspiration from one. Your concern should only be if I am attempting to defraud you, which I'm not. I have tested this and it works. That's all I can say to convince you. Really, all you had to do was test it and talk to me. I have had to work with people who have burned PCBs with a torch and want a refund. If you buy it and it doesn't work then deal with me that way. Starting with accusations is not productive between a buyer and a seller.

There is no confusion. You took well made board and fiddled with it making it worse. Designer is an engineer and several others made the copy and verified design. It is good. Proven.

Removing inside ground planes completely destroyed AC return paths underneath the signals. Pouring ground on top did nothing except added DC return path. Sampling frequency and repetition frequency of signals on DUT doesn't matter. Only rise/fall times matter and even with Arduino pins you can get frequency spectra up to 1 GHz, believe it or not.. Raspberry PI has sub nanosecond edged on it's pins, it's even faster. This induces ground bounce, crosstalk and ringing. Thomas spent time designing this with good signal integrity, and did a decent job of it.  There were some other attempts and they could see spurious pulses and noise that is not there. Not with oz2cpu though. It works well.

Designer doesn't mind you making boards and selling them for those who cannot be bothered to order them by themselves. All you needed to do was make them EXACTLY how they were designed, and somewhere in text give design credits to him... And they would work really well.. And I bet you that someone would mention it here as an good purchase option and you would get additional sales..

[rogersstuart]

@Johnny B Good

I was pondering this for a bit and decided to take a look at the original files. I think I know where the confusion came from.

In his (oz2cpu's) original design there was no ground fill on the top and bottom. If this had been made by simply omitting the inner layer gerber files then it would have not worked. When I edited the files I added a ground pour to the top and bottom to add a continuous ground throughout. If this was a microwave circuit then it would have not been appropriate to do so without net via shielding and recalculating the width of the traces. But for the frequencies involved I feel like it was appropriate and the coupling between the sides is insignificant compared to the input impedance. The only concern you should have is about the ribbon cable. But I do mention in the listing that it was designed for 120 ohm cable and that I did not include it, so I feel like I was being fair by mentioning that.

I don't want to get into an argument about international law here. Suffice it to say, I am well within my rights to reproduce a non-patented hardware design or take inspiration from one. Your concern should only be if I am attempting to defraud you, which I'm not. I have tested this and it works. That's all I can say to convince you. Really, all you had to do was test it and talk to me. I have had to work with people who have burned PCBs with a torch and want a refund. If you buy it and it doesn't work then deal with me that way. Starting with accusations is not productive between a buyer and a seller.

You're advertising: Siglent SPL2016 Compatible DIY Logic Probe
That it certainly isn't ! ! !

While it may fit a SDS2000X+ DSO and behave similar to SPL2016 it can in no way challenge the original performance.
Best you have a squiz at the specs here:
https://siglentna.com/wp-content/uploads/2021/05/Digital-Probe-Datasheet-V20E201912.pdf

FYI, original SPL2016 are supplied with 20 quality grabbers and not some POS grabber that falls of if you sneeze on it.
Offering a cheap low level substitute DIY MSO probe that fits a SDS2000X Plus would be well advised rather than mention of SPL2016.

Siglent SPL2016 Compatible DIY Logic Probe

Think please.

[AVGresponding]

Calling something "compatible" implies a matching of capabilities.

When one finds oneself at the bottom of a deep hole, it is usually advisable to cease digging.

[tautech]

@Johnny B Good

I was pondering this for a bit and decided to take a look at the original files. I think I know where the confusion came from.

In his (oz2cpu's) original design there was no ground fill on the top and bottom. If this had been made by simply omitting the inner layer gerber files then it would have not worked. When I edited the files I added a ground pour to the top and bottom to add a continuous ground throughout. If this was a microwave circuit then it would have not been appropriate to do so without net via shielding and recalculating the width of the traces. But for the frequencies involved I feel like it was appropriate and the coupling between the sides is insignificant compared to the input impedance. The only concern you should have is about the ribbon cable. But I do mention in the listing that it was designed for 120 ohm cable and that I did not include it, so I feel like I was being fair by mentioning that.

I don't want to get into an argument about international law here. Suffice it to say, I am well within my rights to reproduce a non-patented hardware design or take inspiration from one. Your concern should only be if I am attempting to defraud you, which I'm not. I have tested this and it works. That's all I can say to convince you. Really, all you had to do was test it and talk to me. I have had to work with people who have burned PCBs with a torch and want a refund. If you buy it and it doesn't work then deal with me that way. Starting with accusations is not productive between a buyer and a seller.

You're advertising: Siglent SPL2016 Compatible DIY Logic Probe
That it certainly isn't ! ! !

While it may fit a SDS2000X+ DSO and behave similar to SPL2016 it can in no way challenge the original performance.
Best you have a squiz at the specs here:
https://siglentna.com/wp-content/uploads/2021/05/Digital-Probe-Datasheet-V20E201912.pdf

FYI, original SPL2016 are supplied with 20 quality grabbers and not some POS grabber that falls of if you sneeze on it.
Offering a cheap low level substitute DIY MSO probe that fits a SDS2000X Plus would be well advised rather than mention of SPL2016.

Siglent SPL2016 Compatible DIY Logic Probe

Think please.

I think NOT !

This same PCI-e design is used by Tek, LeCroy, Rigol and probably others too, all with specs that your DIY version cannot duplicate.
Yes, it's a DIY MSO probe that fits SDS2000X+ models for the purpose of this thread but SPL2016 is in a totally different class.

[rogersstuart]

@Johnny B Good

I was pondering this for a bit and decided to take a look at the original files. I think I know where the confusion came from.

In his (oz2cpu's) original design there was no ground fill on the top and bottom. If this had been made by simply omitting the inner layer gerber files then it would have not worked. When I edited the files I added a ground pour to the top and bottom to add a continuous ground throughout. If this was a microwave circuit then it would have not been appropriate to do so without net via shielding and recalculating the width of the traces. But for the frequencies involved I feel like it was appropriate and the coupling between the sides is insignificant compared to the input impedance. The only concern you should have is about the ribbon cable. But I do mention in the listing that it was designed for 120 ohm cable and that I did not include it, so I feel like I was being fair by mentioning that.

I don't want to get into an argument about international law here. Suffice it to say, I am well within my rights to reproduce a non-patented hardware design or take inspiration from one. Your concern should only be if I am attempting to defraud you, which I'm not. I have tested this and it works. That's all I can say to convince you. Really, all you had to do was test it and talk to me. I have had to work with people who have burned PCBs with a torch and want a refund. If you buy it and it doesn't work then deal with me that way. Starting with accusations is not productive between a buyer and a seller.

There is no confusion. You took well made board and fiddled with it making it worse. Designer is an engineer and several others made the copy and verified design. It is good. Proven.

Removing inside ground planes completely destroyed AC return paths underneath the signals. Pouring ground on top did nothing except added DC return path. Sampling frequency and repetition frequency of signals on DUT doesn't matter. Only rise/fall times matter and even with Arduino pins you can get frequency spectra up to 1 GHz, believe it or not.. Raspberry PI has sub nanosecond edged on it's pins, it's even faster. This induces ground bounce, crosstalk and ringing. Thomas spent time designing this with good signal integrity, and did a decent job of it.  There were some other attempts and they could see spurious pulses and noise that is not there. Not with oz2cpu though. It works well.

Designer doesn't mind you making boards and selling them for those who cannot be bothered to order them by themselves. All you needed to do was make them EXACTLY how they were designed, and somewhere in text give design credits to him... And they would work really well.. And I bet you that someone would mention it here as an good purchase option and you would get additional sales..

I understand the harmonics of a square wave. I think 1 GHz is a bit far out and this isn't a narrow bandpass filter or anything where a high degree of accuracy is needed. If you read the listing I mention that the original design was for 120 ohm cable and that I have included an alternative ribbon cable that worked for me. The component values are as the designer specified.

No one is reading and interpreting. There is just an onslaught of people making assumptions and not testing the reduced cost design. It was too expensive for my tastes to include the inner layers on that tiny board. I don't mention that the extra copper is or isn't included, say where I got it, or provide any implied warranty. Furthermore, I'm not advertising. Don't buy it. It takes up my time. I just like selling things on eBay. It gives me something to do sometimes.

With all that being said, I'm not the kind of guy who won't listen. If you buy one and see that it doesn't suit your needs then just say so. And that's it. It won't damage your scope. If you feel like the signal integrity is bad then what option do I have other than offer you a refund and investigate your claims?

[rogersstuart]

Calling something "compatible" implies a matching of capabilities.

When one finds oneself at the bottom of a deep hole, it is usually advisable to cease digging.

Compatible means that you can plug either into your scope and it will function. I think it's unreasonable to expect identical performance for $20 but if you do, well there are more than 7 billion people out there and everyone is free to have their own opinion.

[Johnny B Good]

@rogersstuart

 I was prompted by oz2cpu's sneaking suspicion that the main PCB may not have been an exact replica of his original 4 layer board and the great importance he places on it meeting this requirement, to verify whether it was a 4 layer board or not. You answered the question honestly and I thank for clarifying that point.

 I sought further advice from oz2cpu before making any decision to cancel the order since your stated eBay policy is "no returns", denying me the opportunity to 'buy and try' as you've just suggested. Cancelling the purchase whilst this was still possible seemed the best option all round and I thank you for deferring to my cancellation request and the speedy refund.

 Since the Belden ribbon cable undoubtedly accounts for most of the high levels of crosstalk shown by the graph you took the trouble to publish, it's impossible to say how much of a problem the lack of the inner groundplane shielding layers would be in this case.

 Since oz2cpu had stressed the importance of a 4 layer PCB, I deferred to his judgement over your claim that this wasn't really that important after all. You may be right but there is no way to prove this, short of actually testing using twisted pair or coaxial cabling between the main PCB and the pods.

 One way around this issue with your version of the main PCB, would be to wire up a pod using twisted pairs or coaxial cables and generate a new crosstalk graph for comparison against the Belden cable you're supplying as a courtesy to those with a more modest initial performance requirement.

 Provided you've made it clear up front that the main PCB is only a two layer version of the original design and spell out your reasons for this cost cutting choice, backed up by the new graphical evidence obtained using twisted pair or coaxial cables, I should think you wouldn't have any further problems in this regard.

 Supplying only a single 'starter pack' of test clip leads isn't such a bad idea since the quality and price of these test clips can vary considerably and it's best to economise here and allow the end user to make their own choice in the price/quality equation.

[rogersstuart]

@rogersstuart

 I was prompted by oz2cpu's sneaking suspicion that the main PCB may not have been an exact replica of his original 4 layer board and the great importance he places on it meeting this requirement, to verify whether it was a 4 layer board or not. You answered the question honestly and I thank for clarifying that point.

 I sought further advice from oz2cpu before making any decision to cancel the order since your stated eBay policy is "no returns", denying me the opportunity to 'buy and try' as you've just suggested. Cancelling the purchase whilst this was still possible seemed the best option all round and I thank you for deferring to my cancellation request and the speedy refund.

 Since the Belden ribbon cable undoubtedly accounts for most of the high levels of crosstalk shown by the graph you took the trouble to publish, it's impossible to say how much of a problem the lack of the inner groundplane shielding layers would be in this case.

 Since oz2cpu had stressed the importance of a 4 layer PCB, I deferred to his judgement over your claim that this wasn't really that important after all. You may be right but there is no way to prove this, short of actually testing using twisted pair or coaxial cabling between the main PCB and the pods.

 One way around this issue with your version of the main PCB, would be to wire up a pod using twisted pairs or coaxial cables and generate a new crosstalk graph for comparison against the Belden cable you're supplying as a courtesy to those with a more modest initial performance requirement.

 Provided you've made it clear up front that the main PCB is only a two layer version of the original design and spell out your reasons for this cost cutting choice, backed up by the new graphical evidence obtained using twisted pair or coaxial cables, I should think you wouldn't have any further problems in this regard.

 Supplying only a single 'starter pack' of test clip leads isn't such a bad idea since the quality and price of these test clips can vary considerably and it's best to economise here and allow the end user to make their own choice in the price/quality equation.

No returns is just a psychological thing and part of doing business on eBay. I do not want to pay for shipping to Europe. There is no such thing as no returns on eBay once someone opens a dispute. I would prefer to leave people feeling satisfied even if that means a loss here or there.

I feel like I should not have responded because the thread has been derailed now. I saw mention of opening a dispute and you sounded upset, so I said something. I was worried that someone might act maliciously assuming that I'm a bad actor out to scam people.

I agree with you about the high level of crosstalk. I'm not sure what it should be. At best it is -15 dBm below 100 MHz, at worst it is -8-7 dBm. Though, I have to admit that I'm not sure if I measured it correctly. I soldered female DuPont connector pins to SMA connectors and measured S21 using my 75 OHM VNA that was calibrated with 50 OHM Rosenberger "standards" in a 50 OHM system impedance to the end of the cable. I had to bend the pins a little and jam them in there. It was pretty sketchy. I have been told by the designer of the 8753E that it is acceptable to mix impedances like this. Recently I have found that adding pads can clean up a trace and improve accuracy. I would measure it that way now and might see a slight improvement.

I also normalized the data from 50 ohms to 120 ohms based on the 120 ohm cabling that is specified. I'm not sure if it was correct to do so.

As someone had mentioned, the clips that I include are the cheap kind. You know, I wish I could provide good ones but I couldn't find a supplier for them at a low enough price. I say that you get 8 but you would actually receive 10 in case 2 are bad. I count out 10 for each bag and inspect them all. It's really just tacked on so someone can immediately test their build. It's just as cheap for you to buy more on Aliexpress as it is for me to. I don't have a specific markup for this product. All I can say is that I'm selling it for at least half of my calculated price so I'm trying not to add extra things or make it more complicated.

[natman69]

I am interested in building the logic probe for Siglent SDS oscilloscope based on this thread project (many thanks to oz2cpu and other forum members for their amazing work  ).
So if someone it is also interested, I suggest to group buy PCB assembled with SMD passive components from JLCPCB or other suppliers.  Maybe also 3D printed enclosures and cables.

[rogersstuart]

I kept thinking about this so I decided to go back and see if I can find better answers. It appears that oz2cpu's design (and the HP design his was inspired by) are meant to form a voltage divider. I used a VNA to generate a model of the digital input to use as termination. I would have preferred to know exactly what components are used internally but I couldn't find a picture of both sides of the scope PCB. It's 10k DC which leads me to believe there's more to it than TVS diodes and the comparators.  I also used measurements of 24" of the ribbon cable I have on hand in a GSG order. All connected by co-simulations of the PCB layouts. I was able to select a reasonable set of values to get a 1/10 voltage divider action and the waveform looked okay. Since this was based on my own measurements and I only have so much confidence in my setup and skills, I admit that there is probably some error. The values provided by oz2cpu produce a squarish waveform in the simulator with a close to 1/6 voltage division which is (for me) good enough to back my assertion that this is meant to be a voltage divider.

As expected, there was some coupling between the top and bottom traces. I isolated a segment from where the 120 ohm resistor is to the card edge. At worst you can expect 6.2% voltage coupling (700 MHz) with a 10k load and near 1.3% at 1 MHz. The amount of signal that makes it through decreases with increasing frequency which affects that number (increase).

I tested swapping the 8.2p capacitor for a 20p capacitor and swapping the 120 Ohm resistors for 100 Ohm resistors. With my function generator referenced to a 10 MHz square wave being generated by my scope I saw little to no difference between the original or either modified component selections. With the 20p capacitor maybe there was a moment of jittering while handling the probe. Of course, this was best case since the sampling should have been fully synchronized with the waveform generator. All this tells us is that the waveform was not distorted enough to be unusable. I did not try swapping the 86.6k resistor. My simulations indicated that a wide range of values (as low as 20k) would work.

To further verify functionality for basic logic analyzer tasks I fed low rate (11520 bps) serial data into the probe. This signal was generated by a FTDI UART. I measured the rise and fall time to be near 10ns. I repeated "hello" 100 times, triggered off of it, and counted the trigger pulses. There were 100 triggers. I followed this by inserting a 200k potentiometer. Across the entire range the scope was able to decode the signal (less reliably at 200k) which is a point where my simulation drastically departs from reality. No glitches or false triggering. This seems to be acceptable.

Every choice you could make has a tradeoff. oz2cpu's design seems pretty flexible. If you are trying to cut costs I can't find a reason why picking a different cable, using slightly different passives, or even making some changes to the layout would prevent this from working. The only way I could break it was by selecting a wildly different set of component values. The voltage divider action or at least some compensation for the reactance seems necessary for this to work properly.

[Slartibartfast]

Calling something "compatible" implies a matching of capabilities.

Not really. Unfortunately that word is far too corrupted by marketing people to mean anything like that specifically.

[gtube]

Hello oz2cpu,
Thanks a lot for your great work and sharing! I just tried to order a couple PCBs from JLC. I just noticed that POD PCB is missing in the thingiverse link below. Only scope plug in PCB is there.  Could you please upload the POD PCB?

Thank you!

ALTIUM AND GERBER FILES ARE NOW IN THE ZIP FILES HERE:

my 3D design files : https://www.thingiverse.com/thing:4784443

[gtube]

I was thinking, instead of twisting and soldering those interconnect wires between POD and PLUG IN PCBs,  how about use CAT8 shielded Ethernet cable which already has 4 twisted pairs inside? Just install two RJ45 ethernet jacks on both PCBs.

[oz2cpu]

the POD files are in the link
try to look at this file
Production_Data_SDS_1.zip

[nall]

Thanks to oz2cpu and others for this design. I finished building my set last night and it seems to be working great!

I have extra PCBs if anyone wants them for cost of shipping -- just PM me. all gone

[Coder69]

Hi,

I have started to check the Gerber-files for the plugin board. I think the board thickness should be
1.6mm and the surface finish ENIG. Especially for ENIG you can choose the gold thickness between
1 U" and 2 U". What do you you recommend ? Is 1 U" enough ?
BTW: Thanks a lot for this project ! 

[oz2cpu]

i ordered my PCB's from JLC and asked for 1.6mm
i also asked for enig, just the cheapes is fine for me,
do you expect to pull it in/out 3 times pr week, the whole year ?
then order the thicker gold :-)

[mnementh]

   

After considerable reading on eevBlog and some time in Frustion360, I've devised an alternate solution which leverages TK's adapter PCB to connect directly to the HP logic probe pods; tautech seemed to quite like the project and suggested I post in here about it, so here's the link:

https://www.eevblog.com/forum/testgear/diy-logic-probes-alternate-approach-using-tks-adapter-pcb/msg4326775/#msg4326775

Cheers!

mnem
 

[rogersstuart]

I recently purchased a 2pF active probe and compared measurements with that to a simulation using VNA measurements and an EM simulation. I found that with an FFC a value of 5.1 pF at the input of the scope leads to a nearly perfect 1/10 voltage divider. There is a little overshoot but not much ringing. The VNA measurement shows almost no ringing which leads me to believe that any ringing is simply a grounding error. The biggest variable in regard to voltage level at the scope input is how much the cable loads the signal. If you intend to use the full range of 10V then I suggest decreasing the value of the capacitor. The quality of the cable does matter but this isn't really the most high speed logic analyzer out there and you will find that the signal jitters around a bit as the specs state in the datasheet regardless of the "quality" of the cable used. 

[aystarik]

Hi,
I've desided I want my own design of the PCB for RF1.37 (https://aliexpress.ru/item/1005003601266058.html) coaxial cables (1 ground pad for each input) :   and also make it more "equal". I think I'll try to have input-end 120 ohm resistor directly on the cable, without additional boards -- like here: https://community.element14.com/technologies/test-and-measurement/b/blog/posts/building-solderable-in-circuit-oscilloscope-probes

github repo with kicad project is here: https://github.com/aystarik/siglent-la

[Wahyueko]

I want to make it for my MSO5000

[tautech]

I want to make it for my MSO5000

It has its own thread dedicated to DIY logic probes.
Use the forum search.

[Wahyueko]

yes I've tried searching, I want to try to assemble this logic probe. now I have printed the pcb to the pcb manufacturing factory.

[tautech]

yes I've tried searching, I want to try to assemble this logic probe. now I have printed the pcb to the pcb manufacturing factory.

It will not fit MSO5000.

Please go here:
https://www.eevblog.com/forum/testgear/low-cost-logic-analyzer-probe-for-rigol-mso5000-easyeda-project/

[Wahyueko]

Big thanks sir,
I used the Tektronix mso5204 logic probe which is compatible with p6616, but the price is quite expensive.
not rigol mso5000

[Wahyueko]

I have already printed the PCB, I hope you can, sir.

[rogersstuart]

I have already printed the PCB, I hope you can, sir.

Did you make it 2 layers without adding a ground pour? If so, you would need to reorder them anyway. The probe in this thread is not designed for the MSO5000. The Siglent scopes have all of the digital probe active electronics inside the scope. The MSO5000 series needs (at the bare minimum) external LVDS line drivers to work properly. Get on chat with JLCPCB and see if they can dispose of the PCBs you ordered and refund your shipping. There are multiple people on eBay selling the MSO5000 probes. Just go order one of those.

[Wahyueko]

The pcb arrived, it's not compatible with MSO5000 Tektronix, hehe.
now I'm trying to measure the dimensions of the pcb and the plate in it. all have 40 pins. after I measured it looked like there was indeed a 16-pin signal. 17pin Ground, 1pin NC, 2 pins I measured to gnd the resistance read 110Ohm BDV 0.1V, and 4 pins resistance to ground 10k Ohm BDV 0.58V. and I try to make it again. I don't know what the 2 pins and 4 pins are for and 1 NC pin.

[Uppic]

Hi, I have recently retired and taken up my hobby. They gave me a PM3885 that was cornered in a storage room, but without cables. The question is, could this pod probe serve me for the Philips PM3585. thank you very much to all.

[oz2cpu]

>could this pod probe serve me for the Philips PM3585.

NO

[julian1]

This question is not specifically about the DIY version (have one ordered), but this thread has the most SPL2016 info/knowledgable.

If one wanted a dedicated 2x8 or 1x10 IDC pcb connector, to plug the SPL2016 LA cable directly,

What termination/passives are needed to match the pod/flying lead assembly - if anything?

I measure 91R series resistance, for the pod/flying leads. 

Note, Siglent support this configuration when direct connecting their LA test generator board (see Defpom http://youtu.be/X_cVpH7GLtI?t=88 ).

[julian1]

I found a close-up pic of the Siglent pattern generator that supports a directly connecting to a pcb idc header. There don't appear to be any passives used near the connector.

[teddychn]

Rob,

Thanks for the data, here's what we came up with as a quick estimate model of the LA. The Digital Input pulse was manipulated to try and create what we think the actual pulse to the LA looks like, and show the offset as shown on your DSO measured trace above.

The Digital Probe wire self inductance is based upon 200 & 150mm of #26 AWG wire, the 1100mm coaxial cable (shown as twisted pair in schematic) is modeled as having a Zo of 45 ohms and delay of 6.1ns based upon a velocity factor of 60%. Later we'll need to see how the twisted pair cable (and ribbon) rather than the coaxial cable effects these simulations.

Hi Mike,

This thread is informative. I'm trying to adapt my existing 54622D logic probe to SDS2104X HD and conduct some simulations concurrently. However, I'm not sure what R1 and C2 in your simulation represent. Have you already known the impedance model of the SDS2000X Plus/HD logic port?

Thanks,
Ted

[mawyatt]

Rob,

Thanks for the data, here's what we came up with as a quick estimate model of the LA. The Digital Input pulse was manipulated to try and create what we think the actual pulse to the LA looks like, and show the offset as shown on your DSO measured trace above.

The Digital Probe wire self inductance is based upon 200 & 150mm of #26 AWG wire, the 1100mm coaxial cable (shown as twisted pair in schematic) is modeled as having a Zo of 45 ohms and delay of 6.1ns based upon a velocity factor of 60%. Later we'll need to see how the twisted pair cable (and ribbon) rather than the coaxial cable effects these simulations.

Hi Mike,

This thread is informative. I'm trying to adapt my existing 54622D logic probe to SDS2104X HD and conduct some simulations concurrently. However, I'm not sure what R1 and C2 in your simulation represent. Have you already known the impedance model of the SDS2000X Plus/HD logic port?

Thanks,
Ted

Hi Ted,

These (R1 and C1) were used to attempt to mimic the Siglent response tautech had shown earlier, check the thread prior to the one this schematic originated from. You can see the simulated response and compare to the one tautech posted.

We used twisted pair for the signal lines and later just ribbon cable, recall both worked well for our needs, memory's not that good tho 

Anyway, at one time we were going to "tweak" the component values for optimum response but never needed to do such, as it worked well enough for our needs right from the start as shown, so we've never revisited this since.

Best,

[teddychn]

Thanks Mike,

After some trials, I found that the cable length has a significant impact because the transmission line impedance doesn't perfectly match the LA's input impedance. I'm starting by inserting a 75-ohm resistor at the front end of the microstrip line of the adapter. I feel the front end resistor of the LA adapter in your picture seems to be ferrite beads, am I right?

[mawyatt]

No ferrite beads were used, just R and Cs I recall.

Best,

[KungFuJosh]

I bought one of the DIY type LA probes on eBay for $40 shipped. It worked great in the Batronix MSO board tests. I assume the seller is a member of this site.

[mawyatt]

Likely copies of Thomas (oz2cpu) original work, not sure if authorized or not. As clock speeds increase the details of the probe begin to show, this includes the type and nature of the cables utilized. These are improper terminated cables on both ends, either coaxial, twisted pair, or ribbon type with SGSG configuration.

Tautech kindly provided what the OEM Siglent Probes waveforms looked like, so we attempted to duplicate that performance blindly, meaning not knowing about the details inside the DSO case, and created a model for what we "thought" might be a good representative, proof being did the simulation waveform resemble the tautech provided actual waveform.

So we created our version based upon this and planned to "tweak" the component values and such to optimize the performance. We never got around to this optimization tho, as the 1st cut performed well enough for our needs at the time, and we haven't had a need to revisit this for improved behavior.......yet 

Best,

[KungFuJosh]

So we created our version

Gonna share? 😉

[mawyatt]

So we created our version

Gonna share? 😉

All listed within this thread

Best,

[KungFuJosh]

Likely copies of Thomas (oz2cpu) original work, not sure if authorized or not.

Well, now that I've read the thread, I know who the seller was. It did work well on the MSO demo board. 🤷

[tautech]

These (R1 and C1) were used to attempt to mimic the Siglent response tautech had shown earlier, check the thread prior to the one this schematic originated from. You can see the simulated response and compare to the one tautech posted.

We used twisted pair for the signal lines and later just ribbon cable, recall both worked well for our needs, memory's not that good tho 

Anyway, at one time we were going to "tweak" the component values for optimum response but never needed to do such, as it worked well enough for our needs right from the start as shown, so we've never revisited this since.

Best,

Now I have new and better SMD tweezers (ST42) I can do these measurements again if required including mainboard input measurements on a warranty replacement board.
Maybe these is a termination network there too that could help with a better match.

Tell me what you need. 

[teddychn]

Maybe these is a termination network there too that could help with a better match.

You're very possibly right. Here's the information in the 54622D manual:

[KungFuJosh]

I want to build oz2cpu's version intended version of this. Is there a limitation to the length of the wires used? And what's the best wire for use with this?

Thanks,
Josh

[tautech]

I want to build oz2cpu's version intended version of this. Is there a limitation to the length of the wires used? And what's the best wire for use with this?

OEM are 1M long 8ch pairs of micro-coaxial ribbon cable.

Find one from another brand and modify it as Defpom did here:
https://www.eevblog.com/forum/testgear/diy-logic-analyzer-probe-and-pods-for-siglent-scopes/msg3691729/#msg3691729

[KungFuJosh]

Has anybody tried shielded ethernet cable? It's 4 sets of twisted pairs (2 per pod). Cat6A is rated up to 500MHz. Regular Cat6 is rated 250MHz, and Cat7 and Cat6E are rated for 600MHz. Cat8 is rated for 2GHz. Aren't all of those beyond the capability of the DIY adapter?

[Martin72]

Hi,
I´ve bought the original SPL2016 and post it in the Siglent HD thread, with pics.
https://www.eevblog.com/forum/testgear/siglent-sds2000x-hd-12bit-(published-for-chinese-domestic-market-only)/msg4997911/#msg4997911

Now you must do a battle with the clone version.

Clone version...I don´t know a clone version(where to buy), but If I can help finding things out I´ll do (except opening something).
Got the STB-3 demoboard and the batronix demoboard here, if I should measure something with them, let me know.

[KungFuJosh]

Clone version...I don´t know a clone version(where to buy), but If I can help finding things out I´ll do (except opening something).

The files (gerbers and 3D print) are available in the first post of this thread. Another project for you to build. 😉

[kripton2035]

I bought my clone on ebay : https://www.ebay.com/itm/225024212937
arrived in france in a few weeks.
at that kind of price I did not bother to build my own.


oh and there was some delay in the shipping, the item seemed to be stuck somewhere
the seller was very kind and responsive.


the hooks are some kind of first price one, but they work. you can buy better one eventually.

[KungFuJosh]

I received the PCBs, but I'm having issues with the 3D parts.

JLC is giving an under 1mm thickness warning for the parts. Did anybody else have that issue? Is that correct, or is there something wrong with their system or the 3D models?

Thanks,
Josh

[Martin72]

Got the same message from the 3D parts of the voltage reference (not the heater case).

[KungFuJosh]

Got the same message from the 3D parts of the voltage reference (not the heater case).

Me too, that's partly why I'm concerned. I hope it's not a design file compatibility issue with JLC.

Did you get the parts in yet?

[Martin72]

I wanted to fix the criticized positions first, because e.g. the front panel for the display is actually thinner than 0.8mm, so I had canceled everything.
Most parts were titled as OK.

[TERRA Operative]

Ok, my turn to make one of these.... Was any further development done to improve the performance or is as it stands good enough?
Did anyone ever take a look inside the Siglent probe?

I think I wouldn't mind having a go at modifying the design a little to match the Siglent with the way the probes attach, maybe using some 2.54mm rectangular header sockets.

[tautech]

thanks a lot mate, that saved me a lot of trouble :-)

could have been cool if only they existed in correct color codes from 0 to 9
so i have to find a way to add a label, and if they are colored at the same time, i end up being confused
since i cant turn off my brains color decoder

Coloured LA/MSO channel tabs are being rolled out into all models that support MSO.
Then if you have coloured grabbers you might be able to match them up to the displayed tabs. 

[TheDefpom]

Then if you have coloured grabbers you might be able to match them up to the displayed tabs. 

Damnit, now I need to buy coloured grabbers...

[tautech]

Then if you have coloured grabbers you might be able to match them up to the displayed tabs. 

Damnit, now I need to buy coloured grabbers...

Link listed in my reply #13, long expired but the ePay listing description might help with a search.
Be sure to get the same style as OEM for best holding power.
Pics here:
https://www.eevblog.com/forum/testgear/diy-logic-analyzer-probe-and-pods-for-siglent-scopes/msg3496458/#msg3496458

[KungFuJosh]

Are you referring to the E-Z Hook brand grabbers? I have them in my list: https://www.amazon.com/dp/B00R3R7IVC/

[TheDefpom]

Damn, those aren't cheap.... so I only got 2 pairs, you always need a spare.

[tautech]

Are you referring to the E-Z Hook brand grabbers? I have them in my list: https://www.amazon.com/dp/B00R3R7IVC/

Perfect. 
10 for $34 is well priced compared to the 10 lot of Tek grabbers a mate and I shared 20 yrs back, they were $5ea !

[tautech]

Another bit cheaper $21 set linked by ePay:
https://www.amazon.com/10PCS-Grabber-Jumper-Analyzer-Colors/dp/B083PRVPCR/ref=pd_vtp_h_pd_vtp_h_d_sccl_3/143-5889884-9612055?

[ebastler]

Another bit cheaper $21 set linked by ePay:
https://www.amazon.com/10PCS-Grabber-Jumper-Analyzer-Colors/dp/B083PRVPCR/ref=pd_vtp_h_pd_vtp_h_d_sccl_3/143-5889884-9612055?

Wrong colors though, if you are after a match with the new SDS display.

[KungFuJosh]

Another bit cheaper $21 set linked by ePay:
https://www.amazon.com/10PCS-Grabber-Jumper-Analyzer-Colors/dp/B083PRVPCR/ref=pd_vtp_h_pd_vtp_h_d_sccl_3/143-5889884-9612055?

I wouldn't trust those, especially not for the $10 savings. Some of the reviews mentioned the springs failing, or the grabbers being too soft metal to properly hold things.

[fredo_]

Hi there,
Did anyone try the PCB Assembly service of JLCPCB for oz2cpu's design ?
Maybe someone as working BOM and CPL files ?

[fredo_]

Well I'm proud to join the team of oz2cpu's design probe owners ! 
I ended up ordering on JLCPCB with PCB assembly (single side). Boards arrived with half the 120R resistor soldered on the scope board (upper side) and the 86K6 and 120R soldered on the pod boards :

Soldering the missing 120R resistors and the 8p2 caps stacked on top of the 86K6 resistors was not a simple task for me, as it was my first time doing SMD stuff
I ended up doing it with solder paste and an hot-air gun (couldn't make a clean work on 0603 parts with a soldering iron...)
Everything works as expected (tested with an ESP32 board providing approx. 10Mhz output)  :

[fredo_]

I ended up ordering on JLCPCB with PCB assembly (single side).

In case someone needs it, here are the BOM and pick and place files I used.

[mawyatt]

Ok, my turn to make one of these.... Was any further development done to improve the performance or is as it stands good enough?
Did anyone ever take a look inside the Siglent probe?

I think I wouldn't mind having a go at modifying the design a little to match the Siglent with the way the probes attach, maybe using some 2.54mm rectangular header sockets.

If you go back and start searching with our inputs (like #72 or earlier then onto #138) we posted a version of Thomas's that included the ability to mimic the responses that the OEM Probe produces after modeling the probe with Rob's help. Our version worked well from the start with both twisted-pair ribbon cable and simple ribbon cable (didn't have any micro-coax) that we never followed up on optimizing the probe & cables.

This might be a good start if one wants to squeeze the most out of these probes.

Best,