Author Topic: How to activate IBASIC on vintage HP 871XB network analyzers  (Read 1612 times)

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Offline TK

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Some time ago I purchased an HP 8713B with no software options.  I found information about reprogramming some bytes on the flash ROM to activate all software options and convert the 8711 to 8712 (VNA) and 8713 to 8714 (VNA):

https://www.eevblog.com/forum/testgear/enable-those-extra-features-on-your-hp-8714c-network-analyzer/

The instructions are for the HP 871XC series and it works on the HP 871XB series except for IBASIC which requires a PAL chip (marked as U137 GAL16V8 on the CPU schematics).

So I had the 8713B converted to 8714B, but no IBASIC.  So I started my quest to have IBASIC on my VNA.  The other day I scored another HP 8714B that included the IBASIC U137 PAL chip.  The PAL chip seems to have security bits programmed, and cannot be copied directly using miniPro.  I connected my logic analyzer and I found out what the VNA expects as output of the PAL chip.  It just wants the sequence of characters I B A S i C \0.  The PAL (GAL16V8) chip defines pin 1 as clock and pin 11 as OE when operating in registered mode (flip flops), so I grabbed some old GAL16V8D, GAL16V8B and GAL16V8 chips on eBay and started to learn about PAL programming. 

Using PALASM tool running on a DOSBOX image, I was able to recreate the state machine that HP used to generate the sequence "IBASiC".  Before getting to the idea that was a state machine, started exploring the possibility of some crypto algorithm, but I noticed that it only had 9 clock transitions and 8 OE activations... impossible to implement any type of shift operation using only 9 clock transitions and generate 8 character sequence output, So it must be something very simple... like some basic logic mask using the input to generate the output.  Reviewing the PALASM manual, I realized it must be a MOORE STATE MACHINE.

For anyone interested, I wrote the following state machine in PALASM:

Code: [Select]
;-------------------------------------------------------------------;
;   IBASIC PAL chip clone                                           ;
;-------------------------------------------------------------------;
;                                                                   ;
;                                                                   ;
;                                                                   ;
;-------------------------------------------------------------------;

;PALASM Design Description

;---------------------------------- Declaration Segment ------------
TITLE    IBASIC
PATTERN  A
REVISION 1.0
AUTHOR   TK
COMPANY
DATE     07/05/17

CHIP   IBASIC PAL16V8

;---------------------------------- PIN Declarations ---------------
PIN  1          CLOCK                COMBINATORIAL             ; INPUT
PIN  2          I0                   COMBINATORIAL
PIN  3          I1                   COMBINATORIAL
PIN  4          I2                   COMBINATORIAL
PIN  5          I3                   COMBINATORIAL
PIN  6          I4                   COMBINATORIAL
PIN  7          I5                   COMBINATORIAL
PIN  8          I6                   COMBINATORIAL
PIN  9          I7                   COMBINATORIAL
PIN  12         Q7                   REGISTERED                ; OUTPUT
PIN  13         Q6                   REGISTERED                ; OUTPUT
PIN  14         Q5                   REGISTERED                ; OUTPUT
PIN  15         Q4                   REGISTERED                ; OUTPUT
PIN  16         Q3                   REGISTERED
PIN  17         Q2                   REGISTERED
PIN  18         Q1                   REGISTERED
PIN  19         Q0                   REGISTERED

;-----------------------------------State Segment ------------------
STATE
MOORE_MACHINE
DEFAULT_BRANCH STATE0

;TRANSITION EQUATIONS------------------
STATE0    :=  S0S1       -> STATE1
STATE1    :=  S1S2       -> STATE2
STATE2    :=  S2S3       -> STATE3
STATE3    :=  S3S4       -> STATE4
STATE4    :=  S4S5       -> STATE5
STATE5    :=  S5S6       -> STATE6
STATE6    :=  S6S7       -> STATE7
STATE7    :=  S7S0       -> STATE0

STATE0         =   Q7 *  Q6 *  Q5 *  Q4 *  Q3 *  Q2 *  Q1 *  Q0
STATE1         =  /Q7 * Q6 * /Q5 * /Q4 * Q3 * /Q2 * /Q1 * Q0
STATE2         =  /Q7 * Q6 * /Q5 * /Q4 * /Q3 * /Q2 * Q1 * /Q0
STATE3         =  /Q7 * Q6 * /Q5 * /Q4 * /Q3 * /Q2 * /Q1 * Q0
STATE4         =  /Q7 * Q6 * /Q5 * Q4 * /Q3 * /Q2 * Q1 * Q0
STATE5         =  /Q7 * Q6 * Q5 * /Q4 * Q3 * /Q2 * /Q1 * Q0
STATE6         =  /Q7 * Q6 * /Q5 * /Q4 * /Q3 * /Q2 * Q1 * Q0
STATE7         =  /Q7 * /Q6 * /Q5 * /Q4 * /Q3 * /Q2 * /Q1 * /Q0

CONDITIONS
S0S1 = /I7 * /I6 */I5 * I4 * I3 * /I2 * /I1 * I0
S1S2 = I7 * I6 * I5 * /I4 * I3 * I2 * I1 * /I0
S2S3 = /I7 * /I6 * /I5 * I4 * /I3 * /I2 * /I1 * /I0
S3S4 = I7 * I6 * I5 * /I4 * I3 * /I2 * /I1 * I0
S4S5 = /I7 * I6 * I5 * I4 * I3 * I2 * I1 * /I0
S5S6 = /I7 * I6 * /I5 * I4 * I3 * I2 * I1 * I0
S6S7 = I7 * I6 * /I5 * I4 * I3 * I2 * /I1 * I0
S7S0 = /I7 * /I6 * I5 * /I4 * /I3 * /I2 * I1 * I0

I used a GAL16V8 chip.  Do not use GAL16V8D or GAL16V8B as they have active pull-ups on the I/O pins and when OE is HIGH, output is HIGH and not High-Z.  The old GAL16V8 chip does not have active pull-ups. 

PALASM takes the source code and generates a JED file that can be used with miniPro to program the GAL16V8 chip.

Now I have IBASIC and learned something about PAL and GAL programming

EDIT 19-MAY-2019:  Attached IBASIC.JED.txt  Download and rename as IBASIC.JED
« Last Edit: May 19, 2019, 12:38:38 pm by TK »
 
The following users thanked this post: TheSteve, rogermanlleu


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