So, I read out the 25 spi flash Winbond 25Q16BVSIG flash chip.
Content attached. Did cursory review, some patterns, some empty space, some high density data.
What I would like is if someone with a 2.9 or 3.2 or even also 3.2.1 model to also do this, so we can check if indeed there are only settings in the FLASH.
Presumably waveforms are all the same between 2.9 and 3.1, so if there are only very little changes, it would point to calibration.
Similar for 30MHz models.
However, (should not need to mention it on this forum, but do so anyway) this is at your own risk. I am not responsible for you messing up your device.
Please note that I think the flash is not all the firmware. The display board ARM SoC also has internal flash. It is quite possible these 2 are not always compatible when different versions.
But waveforms is definitely be in the flash, likely also the Cyclone, but probably not the UI programming or the user settings.
Posted some more on Winbond flash memory map
here.
Used a
cheap CH341A clone SPI programmer . See this video (not mine)
tool download link in videoWarning: not all CH341A clones are 3.3V. Ensure you have one that can be properly set to 3.3V.
Note that depending on the clone, you need to pay attention to chip orientation. Both the program icon and the video instruction did not match correct orientation for my programmer clone (I have the exact one of the link above, but there seem to be 2 or 3 more variants.
So look at the silkscreen, use the 25x position for this Winbond chip.
FY6600 Programming header (Cyclone header):
1 | CLK | GND | 2 |
3 | DONE | Vcc | 4 |
5 | /CFG | /CE | 6 |
7 | DO | /CS | 8 |
9 | DI | GND | 10 |
Pinout mapping:
JTAG | FPGA | FLASH | | |
1 | 12 | 6 | CLK | |
2 | | 4 | GND | |
3 | 92 | | Conf_Done | Pulled up with 10K |
4 | | 8 | Vcc | |
5 | 14 | | nConfig | Warning, low can clear the FPGA? Is pulled high by 10K |
6 | 21 | | nCE | When high FPGA disable in tri-state |
7 | 13 | 2 | DO / Data0 | |
8 | | 1 | /CS | When high FLASH disable in tri-state |
9 | 6 | 5 | DI / ASDO | |
10 | | 4 | GND | |
To program Cyclone IV:
- Instructions to be interpreted by a Cyclone expert, being someone else then me
- Keep /CS from Winbond HIGH to disable Winbond Flash
- Pins CLK, /CFG,/CE, DO, DI, DONE have Cyclone functions DCLK, nConfig, nCE, Data0, ASDO, Conf_Done
- Use ByteBlaster II or USB Blaster 10-pin header
To program Winbond:
- Ensure 3.3V or lower programming level
- Connect GND, but Vcc is probably not needed (already fed from FY6600)
- Warning, never make /CFG or nConfig from Cyclone low,
as this may clear the Cyclone maybe best not to even wire the /CFG pin.
- Keep /CE from Cyclone HIGH to disable the Cyclone
- Connect CLK, DO, DI, /CS to SPI programmer (or keep CS low)
- WP and HOLD are already connected high on the FY6600 board
Winbond Cable FY6600-JTAG to DIL-8 emulated chip footprint:
- Loop /CE to Vcc. /CE is normally 10K to ground, so must be lower impedance to Vcc
- Connect GND, CLK, DO, DI, /CS to SPI programmer
When you connect the cable the Cyclone IV FPGA will not start up because nCE is looped high to Vcc. Not even if the other end of the cable is not connected. But the FY6600 does does show its logo. I guess the logo is burned into the screen driver rather then driven by the FPGA
Cable for Flash read/write
WARNING: I wrote this down incorrectly and swapped in 4 and 6. Sorry. Correct now.JTAG | DIL-8 | |
1 | 6 | |
2 | 4 | |
3 | | |
4 | | loop to 6 |
5 | | |
6 | | loop to 4 |
7 | 2 | |
8 | 1 | |
9 | 5 | |
10 | | |
Edit: While analyzing the firmware, I made some interesting new finds:
More detailed
info here, but a summery:
The programming header is a standard Cyclone USB Blaster II header, see newly attached image.
Also, I now believe the first x05ffff bytes of the flash are the Cyclone configuration bitstream. The cyclone itself reads this without the intervention of a CPU, as
shown in this document.Flash structure:
0x000000 Cyclone bitstream
0x060000 Most build in waveforms (not in 1:1 mapping) (the ones repeating in Arb).
0x100000 Arb1~64 in blocks of x4000 bytes (first 32 a repeat of 0x060000)
There is likely no user settings or calibration in the flash. I changed settings, and reread, and nothing was changed.
So user settings are likely stored in SoC on the display board, which controls the Cyclone by simply serial commands.
In other words, the SoC has the User UI firmware, that is not stored in the Winbond flash, and we need to retrieve that too.