Hello for everybody! It's my first post on the forum and in this thread. Sorry in advance for my poor English, not my native language.
I've been reading this thread since I decided to order FY6600 in the beginning of the year, a lot of useful infos here!
I have got my unit at February 16, played with it and now decided to join to the forum and to this thread particularly.
First some remarks about the generator as is without any modification. I got it from ebay (echoii_shop), luckily version 3.2, board revision 1.501.
The generator works normally with quite decent calibration: 5.04Vp-p , 30mV offset (5Vp-p, 0V offset, 10kHz sine settings).
The timebase is a pretty accurate also: -4 ppm after 30 min warm-up with +/-100 ns jitters, planning upgrade generator anyway.
An interesting thing is the switching power supply. As I can see it is a new variant. It has the same problem of leakage current: 90Vac relative PE (my mains is 230V).
But when I measured output voltages I was surprised: +5V under load was exactly +5Vdc (4.9976Vdc on my Fluke 289), and higher voltages were +12.04Vdc
and -12.08Vdc . In standby mode voltages were +5.0000V
, +11.877V and -11.940V respectively. And absolutely no adjustment components in the unit
!
So no dangerous output voltages in any mode. I check output pulsations, 30mVp-p on +5V bus that is well enough and much worse 300mVp-p on +/-12V buses.
Think I could live with this PSU after modifying it to eliminate the leakage current problem of course.
Now more interesting part of my post
. I am a quite experienced designer of FPGA based systems, particularly of Altera's repertoire.
So I can make a few educated conclusions about main board of the generator.
1. As someone already found CycloneIV get its configuration from Winbond's flash and this configuration data is located in the beginning of the chip. Judging by its size
configuration data are uncompressed. Configuration for Altera's FPGA can be in compressed form that may occupy 30-50% less of memory if we decide to make our own design.
No problems to write a new configuration by USB interface through the front panel MCU as FPGA has full access to the flash. There're two possibilities:
MCU can rewrite a portion of the flash with configuration data (if I got it right MCU can write into flash addresses) they are not used after configuration was load.
But if something goes wrong we get a brick that can be revived only by programming flash with a dedicated cable. So more advanced perspective.
CycloneIV has remote upgrade mode. In it there are few configurations: one factory one that is never erased and one or more application configuration. The factory configuration is
load on power-up reset and after it can load any specified application configuration. This process can be controlled by FP MCU. If loading of the application configuration fails
the chip returns to the factory configuration with indication of a reason for error. So the factory configuration can be used for writing a new working configuration into the flash
and starting this new configuration after it or after power-up reset. In this case we will always have a fallback procedure if something goes wrong.
And now main question: for what could we be wanting to modify generally quite good design? Some thoughts.
2. We can enhance square wave generation providing settings for rise/fall times. Concerning 4ns jitters of edges not much can be made here as PLL circuit in the chip is quite limited,
it can provide frequency Fref *M/N where M,N=1..512, too coarse for any decent frequency resolution. CycloneV has fractional PLLs which could provide a frequency resolution of
order of a part of a Hertz in our case but we have CycloneIV
.
3. But PLL in CycloneIV allows easily to use TXCO quartz generator of 10MHz that can facilitate upgrade to external 10MHz precision time reference. Moreover the PLL in CycloneIV can be
reprogrammed in running chip without reloading of configuration, so we can adjust the same configuration for different reference clocks by MCU in working system.
4. We can add new functions. In the flash can be written a stream of bits (128K at most) instead of an ARB waveform. And that stream can be output as CMOS pulses or any other pulses bit by bit
with set frequency, amplitude and etc or used as modulating signal for carrier signal (ASK? FSK and so on). It would be useful for testing and debugging digital systems particularely
digital data transmission ones.
5. Use sigma-delta modulation to get more resolution from DAC when generating lower frequency signals. But I am not sure here as DACs are already overclocked
and might have not very good linearity. This requires additional investigation, unfortunately I haven't got relevant test devices for it.
6. Something else....
If there is an interest in the community I could contribute to such efforts.
Home
Help
Search
Login
Register
