FeelTech FY6600 60MHz 2-Ch VCO Function Arbitrary Waveform Signal Generator

[zov]

Remember there is two channels. So that would be all 32KB used up, with not a single byte left for anything else.

I do not know much about FPGA, but maybe those registers and stuff are not RAM, but CLB & IOB states, and not counted toward its memory?

I forgot about second channels  thank you! So no memory left for any other tasks. Implementing memory in LABs (it is equivalent to CLB in Altera's parlance) is too costly from resource point of view.
BTW it is only 6000 LE in the used chip so no more then 6 kbit can be implemented.

Considering your remark about 2nd channel I need rethink my plans for implementation somehow.

[cybermaus]

Considering your remark about 2nd channel I need rethink my plans for implementation somehow.

Not sure how serious you are with FPGA redevelop, but if you have that in you and memory is an issue: I for one would be quite happy to go from a 8Ksample AWG to a 4Ks AWG if it would give me more features like: sweep trigger in/out, External sync in/out, etc. Or the holy grail: no jitter (though as you mentioned, not really possible, but you did mention N/M clock ratio's, so with intelligent scheme we could increase the number of sweet spots frequencies)

You could even go half/half: 8Ks on channel A, 4Ks on channel b (by reading only every other byte from the flash)

[rhb]

[
Not sure how serious you are with FPGA redevelop, but if you have that in you and memory is an issue: I for one would be quite happy to go from a 8Ksample AWG to a 4Ks AWG if it would give me more features like: sweep trigger in/out, External sync in/out, etc.

Do the external trigger input and sync input and outputs on the back panel not work?  That was the reason I chose it over the JDS.  Mine borked itself before I got that far in my testing.  I for one would hate to give up the longer waveforms as it would lead to more spurs.

However, if there is room in the flash we might be able to select the waveform lengths or generate some of them with the FP  MCU to save space.

Enjoy your vacation Zov.  Your return will be eagerly awaited by all.

[cybermaus]

It was also part of my reason. Mostly VCO (sweep) but also you never know what you need, so sync in/out BNC and TTL output headers.

Turns out those sync in/out are not classic 10MHz sync, but they are to sync two FY6600 to each other.
Its actually what the manual also states. Did not test because I have only one.

Measuring them, it seems to be a simple 1Vpp pulse of the exact frequency of the one you dailed in. One may think that means you can hook up any other generator, but alas, I was unable to make my other generator generate a pulse that this one actually synced to. So it must be rather finicky to set right (I did not try extremely hard)

Of course we currently know how to make a normal 10MHz sync, so referencing to a standard clock is doable. But following an external frequency is not (unless if another FY6600)

To be honest, I am not sure about the trigger in, but there is no trigger out for the sweep start. It would be nice if the Sync-Out (presumably the only output) could be a sweep out, or alternatively, if ch-2 could be both output, and used for the sweep vco.

[zov]

Not sure how serious you are with FPGA redevelop, but if you have that in you and memory is an issue: I for one would be quite happy to go from a 8Ksample AWG to a 4Ks AWG if it would give me more features like: sweep trigger in/out, External sync in/out, etc. Or the holy grail: no jitter (though as you mentioned, not really possible, but you did mention N/M clock ratio's, so with intelligent scheme we could increase the number of sweet spots frequencies)

You could even go half/half: 8Ks on channel A, 4Ks on channel b (by reading only every other byte from the flash)

Frankly speaking no issues with memory for the moment, just held it aside as a reserve but alas .
And a question: what is the point in making square wave or a waveform with step change without jitter?  I have some thoughts how to make a subset of frequency with jitter decreased on order of magnitude (125 ps) but it would be quite limited set  anyway. And because of complexity of  their implementation it would be certainly very remote perspective.

[zov]

It was also part of my reason. Mostly VCO (sweep) but also you never know what you need, so sync in/out BNC and TTL output headers.

Measuring them, it seems to be a simple 1Vpp pulse of the exact frequency of the one you dailed in. One may think that means you can hook up any other generator, but alas, I was unable to make my other generator generate a pulse that this one actually synced to. So it must be rather finicky to set right (I did not try extremely hard)

AFAIK sweep mode in current implementation is under full control of FP MCU, it just change sweep parameter step by step through SPI. Of course it could be made a more intelligent way inside FPGA. No problem to make sync out with an assistance from FP MCU.

Measuring them, it seems to be a simple 1Vpp pulse of the exact frequency of the one you dailed in. One may think that means you can hook up any other generator, but alas, I was unable to make my other generator generate a pulse that this one actually synced to. So it must be rather finicky to set right (I did not try extremely hard)

If i got it right syncing of multiple units is implemented such a way that a master unit set start phase of waveform generation for all slave units which provide their waveform on their internal reference clocks. It could work well enough for frequencies up to units of megahertz but above an error would be quite appreciable.

[cybermaus]

And a question: what is the point in making square wave or a waveform with step change without jitter?  I have some thoughts how to make a subset of frequency with jitter decreased on order of magnitude (125 ps) but it would be quite limited set  anyway. And because of complexity of  their implementation it would be certainly very remote perspective.

Yeah, I was thinking about the same just now.
Came to the conclusion that with 512:512 ratios, you should be able to get a perfect wave for 2.5 digits deep into the frequency selection.
So all XX.YnnnnnMHz frequencies, with all XX and half of the Y, as well as all X.XYnnnnMHz frequencies

How useful?
As I wrote before, the jitter probably does not matter for any actual DUT (unless if you are working really precise stuff)
But it does help a lot it keep your oscilloscope clean and readable, especially in the 5MHz and above range.
Any signal triggered on or based on that jitter makes the screen somewhat difficult to interpret because of the ghost lines.

I currently find myself often selecting exactly those frequencies 10, 12.5, 25, 32.375, for that reason.
Being able to do all XXMHz would make me happy. But is it worth the trouble? I do not know, because I have no idea of how difficult it is.

[zov]

How useful?
As I wrote before, the jitter probably does not matter for any actual DUT (unless if you are working really precise stuff)
But it does help a lot it keep your oscilloscope clean and readable, especially in the 5MHz and above range.
Any signal triggered on or based on that jitter makes the screen somewhat difficult to interpret because of the ghost lines.

And sine signal cannot be used for oscilloscope syncing? They have no jitter for any set frequency at all.

[fremen67]

Well, power stayed on here, so I think you did something wrong.

Only connected 4-wire plus gnd, b14, a1
Same result (both LED solidly on)

Tried 3 startup-modes:
- First power, then USB-UART
- First USB-UART then power
- Both connected, then press reset button
All same result

Also, I had a logic analyzer on the UART, and other then power-on spike, I never got any byte in either direction.

Good news: I had the same problem with my second FY6600. The difference beeing my LA connected on the working one. I disconnected my LA and ... bluepill did not boot anymore....
Oups! I defined /FPGA RDY as floating input and my LA was pulling it down through its input resistance, hiding the problem. No LA, no pull-down...
Here is the modified FW with /FPGA RDY defined correctly as Pull-down input.
Sorry about that.

It works on my second FY6600 like that so I hope this time it will work on yours.
At least your are now 100% sure about your wiring 

[DerKammi]

Good to know, I had a slight suspicion it had something to do with IO mapping

I'll try it this evening, work is making a dent in my free time.

[Kaku]

Greetings from Finland!

I tested the latest hex file. First /FPGARDY & SPI2_MISO grounded to check PC - bluepill communication, this works ok. Then wired FPGA board to BP but this "hangs" BP, led stays on and PC connection does not work. I have 30Mhz v3.1 FY6600.

[cybermaus]

Tested first with the FPGA disconnected, PC connection works
Next with FPGA connected: PC connection still works, even able to sniff the UART (see below, simple freq change) but I am not getting any output on the channels.

Code: [Select]

57 4d 46 30 30 31 30 30 30 30 30 30 30 30 30 30  |  WMF0010000000000
30 0a 0a 52 4d 41 0a 35 30 30 30 30 0a 52 4d 4f  |  0..RMA.50000.RMO
0a 30 0a                                         |  .0.             

I also tried to sniff the SPI bus. During power on, I get a lot of stuff on CLK and NSS, but nothing on MOSI or MISO
When already on, and changing something in PC software, it typically does trigger my LA, but nothing shows on any of the wires.

Of course, running in 20MHz with 256K samples, I only get 13msec, maybe the LA needs to wait longer


To finish up, connected FB again, just to see if I had not blown a pin, but it all still works.


I only have one BP at the moment, the other is in use. Have some underway on the slow boat.
I'll try to hook it up to a display later, to see if SPI works properly on this Bluepill, but I suspect its not a hardware problem.

[fremen67]

Thank you for the feedback. I will flash this evening one of my FY with Rev.3.1 and have a look...
We are getting closer ... and it would have been too easy otherwise

[cybermaus]

Not sure if it matters or helps debug, but often when  I restart, the PC software comes with a new set of beginning parameters
Maybe some noise on the lines? Too many gnd connections, ground loop?

Most common seems Square 10KHz 2Vpp

But also seen on Channel 1:
squr 10KHz 1.5Vpp 0V
sine 60MHz 5Vpp 0V
sine 2MHz 2Vpp 0V
squr 10KHz 2Vpp 0V

[fremen67]

Not sure if it matters or helps debug, but often when  I restart, the PC software comes with a new set of beginning parameters
Maybe some noise on the lines? Too many gnd connections, ground loop?

Most common seems Square 10KHz 2Vpp

But also seen on Channel 1:
squr 10KHz 1.5Vpp 0V
sine 60MHz 5Vpp 0V
sine 2MHz 2Vpp 0V
squr 10KHz 2Vpp 0V

Very interesting indeed. That could be the clue. Could you try to add a 10k pull-up resistor on RX and another 10k pull-up resistor on SPI2_MISO?
(on 3.3V of course).
I will be back in 3 hours. That could help a lot in the meantime.

[cybermaus]

Very interesting indeed. That could be the clue. Could you try to add a 10k pull-up resistor on RX and another 10k pull-up resistor on SPI2_MISO?
(on 3.3V of course).
I will be back in 3 hours. That could help a lot in the meantime.

And it works...
So: 10K pull up to MISO (PB14)

Did not do a pull up to RX (yet)

[cybermaus]

Some testing, actual errors: (just the one)

Chan 1 was set to SQUR, Channel 2 to Sine
I clicked all the sync checkmarks, and though now Channel 2 shows a grayed out SQUR in the PC, it still generated Sine. When stop/start channel 2 it became a SQUR

I assume sweep/mod/counter and fancy stuff like waveform upload are not there yet, right?


Anyway, I made a proper loom, so I can more easily reconnect for next tests.
Basically I took all the single dupont from the clips, and instead grouped them in fixed 3x 4x 5x 8x dupont headers.

[DerKammi]

I just tested mine with a pullup on the MISO line, but no signals on the outputs. The whole interfacing seems to work and I see data on the MISO/MOSI lines with my scope, but no signals out.

You do have outputs Cybermaus?

[cybermaus]

Yes, I have outputs on both channel 1 and 2

It still seems somewhat noise related. Even the first time I had it working, I had to stop and start a few times (power off and on) the device, and then suddenly it worked.
And then after I made my loom again it did not work, and after a few restarts it did. Whenever it does not work, green led stays on.

Key is that green led. If it turns off, you are initialized and it works, outputs nicely follow PC controls.
I think the noise makes it sometimes fail initialization. The pullup helps, but does not eliminate all noise, so its a bit of a try-again game.


You know, I used to work with audio frequencies, and breadboard and ad-hoc wiring is OK. But whenever I try and go about a few MHz, I find that all that spagetti wiring is really disruptive. Stray capacitance, inductance, loops cause all sort of ugly signals.

Here too, I think if we want reliable testing, we should solder a BP to a proper veraboard and proper headers directly for the FY6600 connectors, without any breadboard wiring in between.

PS: with no PC control, the BP seems to send out a channel 1 10KHz 2V square wave by default. So first keep USB unconnected, and turn on/off the FY6600 and/or reset the BP

[DerKammi]

It does indeed. So for further testing I would like to suggest to slow down the SPI clock to the sub MHz region perhaps, this makes wiring a lot easier. Speed is not really an requirement right now.

I'll hit the trial and error hammer a couple of times.

[fremen67]

Some testing, actual errors: (just the one)

Chan 1 was set to SQUR, Channel 2 to Sine
I clicked all the sync checkmarks, and though now Channel 2 shows a grayed out SQUR in the PC, it still generated Sine. When stop/start channel 2 it became a SQUR

Thank you for the feedback. I missed this one. A last minute change. Should be corrected in this release.

I assume sweep/mod/counter and fancy stuff like waveform upload are not there yet, right?

Waveform upload is there and should work.
For sweep/mod/counter no it's not there. Sorry about that but it was already a lot work to get there.

I added internal pull-down for MISO and internal pull-up for RX. With this configuration I have 100% boot up on BP. So you can now remove the externel pull-up resistors and test if it's better or not.

On the other FY with my dev board and the LA connected I never had any failure during boot-up so there must be a way...

[Kaku]

FW version 0.2 tested. Randomly BP starts and then everything works fine. 30MHz unit works at 60MHz, this was really nice to see 

[cybermaus]

New firmware v0.2, still with pullup: started on first try
Removed pullup, started on first try again.

Nice!

[Kaku]

MOSI/MISO screenshots of the situation when BP does not boot.  What did you think about them?

[cybermaus]

Not a SPI guy myself. But some suggestions:

- Lay your wire nice and straight, no spaghetti
- Short wires, no loops, and close together, keep the rainbow-ribbon whole if possible
- Turn off any nearby (cheap) electronics, like LED lights with bad transformers on ungrounded two wire connections

(I had to put my LED drivers into a earthed tin can, to get rid of the noise. And they were expensive local store bought office panels too, not even china. Still looking for better LED drivers)