Products > Test Equipment
REVIEW - Rigol DS2072 - First Impressions of the DS2000 series from Rigol
Jason:
Check out what happens when I select dots.
1) Horizontally the dots are spaced 200ps / 5GHz apart. That's significantly faster than my 1GHz sample rate. That suggests the ADCs might support timing much finer than the sample rate, which might mean the hardware is capable of equivalent time sampling.
2) There are some very tight vertical groups.
Together these suggest that the trigger-out jitter is grouped to some multiple of the ADCs' clock - probably the FPGA's clock. Perhaps the trigger-out logic runs on a divided clock. That's really weird though, since the trigger in seems quite accurate.
Disclaimer: I don't know WTF I'm talking about. :)
Marmad, might you could give us a screen shot of the trigger pulses on dots mode at 2ns/div?
Edit: Note that this also had 500ms of persistence.
marmad:
--- Quote from: Jason on April 30, 2013, 08:54:35 am ---1) Horizontally the dots are spaced 200ps / 5GHz apart. That's significantly faster than my 1GHz sample rate. That suggests the ADCs might support timing much finer than the sample rate, which might mean the hardware is capable of equivalent time sampling.
--- End quote ---
I think you miscounted, Jason. You have 20 dots per div, so 5ns / 20 = 250ps (4GHz or double the max. sampling rate) - which is the same frequency as pointed out previously. I'm guessing that this is perhaps the main clock rate before it's divided.
--- Quote ---Marmad, might you could give us a screen shot of the trigger pulses on dots mode at 2ns/div?
--- End quote ---
I get the same 250ps spacing (8 dots per div at 2ns).
marmad:
--- Quote from: Teneyes on April 29, 2013, 08:44:52 pm ---IF one was to record 32 frames , would there be a regular pattern or random positioning of the traces within the 8 ns ? I think a 3-D plot in ZT would be interesting.
--- End quote ---
Here you go, Len - there is a pattern, but the exact one is difficult to catch since it's happening faster than frame capture rates:
marmad:
--- Quote from: Teneyes on April 30, 2013, 04:53:21 pm ---Yes , I was thinking about that and think that if One feeds in Only a slow square wave = 1/2 the update rate and in NORMAL trigger.
Does minimum Hold-off have an effect? (the HOLD-Off clock resolution )
Also does this 8ns occur when triggering is from Ch1 or Ch2, not sure of EV's CH1 display.
--- End quote ---
If you feed a very slow square wave in, you can watch the pattern more clearly. But the 8ns variation always occurs - doesn't matter about the trigger source, speed, sample size, etc; if you look at the image, it shows the measurement statistics.
The Trigger Out delay falls between ~211 - 219ns (using channel triggering). But the difference (~3.6% of 219ns) is not very relevant because if you want to trigger another device, the initial triggering clock speed can't be more than ~4.5MHz max. (1/220ns) - and if it was 211ns that would still be only ~4.7MHz. So not much difference.
The main point being that for reliably using the DSO to trigger an external device (such as an LA) using the channel triggers, the frequency of the DUT should be <= 4.43MHz.
Edit: If you're just passing the trigger through (using External Trigger In), you might be able to get to 6MHz (1/167ns).
Hydrawerk:
--- Quote ---Who was that on EEVBLOG that has a DS4000?
--- End quote ---
Not sure, if he visits Eevblog, but it should be this man called Connor Wolf:
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