Products > Test Equipment

First picture on EEVblog of the new R&S MXO4 series oscilloscope :)

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Hydron:
Sadly it's hard to get hold of the much more unique PMK 20x probes - these look to be a good balance between input C and attenuation (you can get lower input capacitance in a 100x but at a massive attenuation cost, while the 20x ones are quite a bit lower than the 10x while not throwing too much signal out the window).

jjoonathan:
Speaking of the PMK 20x probes, I always wondered if the 1GHz Tek probes weren't using the same trick to extend bandwidth. Does anyone here have a pair handy to measure?

BU508A:

--- Quote from: Hydron on February 20, 2023, 09:53:48 pm ---Sadly it's hard to get hold of the much more unique PMK 20x probes - these look to be a good balance between input C and attenuation (you can get lower input capacitance in a 100x but at a massive attenuation cost, while the 20x ones are quite a bit lower than the 10x while not throwing too much signal out the window).

--- End quote ---

Seems, the PML series has some 20:1 probes. I've attached the datasheet here as well.



maxwell3e10:
Since MXO4 claims a record in waveform updates/sec, it would be good to know how the update rate changes with the number of channels turned on at the same time and the number of waveform points that is more than the minimum.

nimish:

--- Quote from: luudee on February 11, 2023, 05:07:48 pm ---
--- Quote from: maxwell3e10 on February 11, 2023, 04:25:15 pm ---Somehow people cut much more slack for software than hardware errors. Remember how much bad press Intel got for a division bug in Pentiums. But software and firmware bugs are totally accepted. I wouldn't say that software is intrinsically more complicated than designing and making a big processor. Yet hardware gets more and more powerful while software gets more and more bloated while still having mostly the same functionality.
...

--- End quote ---

Traditionally, a lot more testing and verification has been put in to hardware. I have been doing ASIC design
for over 30 years. I have also done some software development (C/C++).

To manufacture an ASIC, the NRE is anywhere between $1Mil USD, 20 years ago, 180nm node, to about
$10Mil USD, Samsung 8nm node, 4 years ago. Because of the high cost, a lot more effort is being put in to
making HW to be correct the first time. Everything from functional verification, to toggle coverage to various
timing analysis had to be 100%. 

Since FPGAs have taken over a lot of the low-volume market, HW/chip designers have lost the art of making
hardware that works the first time around. We now see "firmware" upgrades that not only include software but
also hardware fixes in FPGA bit streams.

I bet the "freeze" Dave found in the MXO4 is from some FPGA ... the GUI appears to work just fine.

Overall, I believe it has become much less critical to properly verify and test hardware and software, since it
has become so easy to provide and install updates. I still vividly remember the times, when a software update
meant for a vendor to ship two 27xxx EEPROMS which you had to physically replace on a device motherboard.

As such, I believe all equipment we will see in this day and age will suffer from incomplete/faulty HW and SW.
It has become so cheap and convenient to issue a fix at  a later date, that I bet many of these vendors purposely
leave out features and function for a later date. Time-to-Market has become the driving force.

Comparing today's "equipment" to what was manufactured 20 years ago, I believe, the designs were much more
mature, complete and though through 20 years ago that they are today.


luudee

--- End quote ---

Who is taping out an 8nm ASIC for $10M? Can they share their alien technology?

When it costs in the millions for a mask-set respin I'm not surprised SW has to pick up the tab. The issue is that good SWE cost a lot of $ and HW companies simply don't pay enough. Why would you work on hard EDA/firmware problems when you can write JS for 4x the $?

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