Fy6800 vs Fy6900

[Johnny B Good]

If it hasn't already been said, the 4ns "jitter" is just the natural result of a 250 MSa/s fixed clock DDS putting out a square wave with a period that is not a multiple of 4ns.  Sine waves don't have this jitter, so if you need a clock, try a sine wave. 

Does anyone actually have an FY6900 in hand yet? I seriously doubt they've added variable clock or "Magic Pulse" as that would be a major revision and upgrade.

 Since no such feature gets a mention in the manual, I'd say your doubts are well founded. 

 Mind you, when it comes to the output level versus frequency limits specified in all the manuals for the 6600 and 6800 models, they can't be relied on as accurate sources of such information. As far as sine and square waves go, there's no such 10Vpp limit in the 10 to 20MHz range for either of those models despite what was written in their manuals. The 20Vpp limit runs all the way from DC to 20MHz before dropping straight down to a 5Vpp limit from there onward.

 The FY6900 may well do the same, contrary to what is claimed in its manual. If this does prove to be the case, then it may indeed be worthy of consideration provided it isn't burdened with a hefty price premium. Although the 24Vpp spec for DC to 5MHz is more a novelty feature, that and the increase from a +/-10v dc offset to a +/-12v dc offset does strongly imply some sort of PSU upgrade from a (nominal) +/-12v opamp rail supply to a +/-15v rail supply.

 Whilst owners of the earlier models (FY6600 and 6800) will see little to no point in purchasing an FY6900 as an 'upgrade', for anyone else contemplating a cheap two channel function generator as an initial purchase for their hobby workbench, the FY6900 would be an obvious choice over its predecessors, assuming it has the same Vpp limits as its predecessors (aside from the 0 to 5MHz 24Vpp upgrade) and is only marginally more pricey.

 I notice that they've added a cooling fan to this model. Not so much a 'luxury item' as an essential component that should have been part of the earlier models' features from the start. With the FY6800's mains inlet socket upgrade from the cheap and nasty C8 connector that had afflicted the FY6600 to a C14 connector giving access to a protective earth pin for use as a high resistance "Static Drain" connection to eliminate the half live mains leakage without introducing ground loop issues, that takes care of two of the many modifications that had to be applied to the FY6600,

 Although the ground loop issue Feeltech introduced by strapping the BNC shield connections directly to the protective earth still needs a simple resistor mod to correct this mistake, at least the hard work of the original modification needed in the case of the FY6600 has already been done, reducing it to a simple matter of adding a 1 to 10 k resistor to eliminate the ground loop issue and still keep the benefit of half mains live voltage leakage suppression (a 10KR is enough to drop the half mains live leakage potential of circa 110v on a 230v supply to just half a volt).

 If they've finally taken this opportunity to fix their 86 ohm attenuator pad 'skoolboy howler' by updating the BOM to replace just six smd resistors to correct it to a 50 ohm attenuator, this could well be the icing on the cake that might persuade some FY6600 owners (especially those with a 15, 20 or 30 MHz specced model) to "upgrade". However, if Feeltech stay true to form, this remains an unlikely prospect.

 With all of those observations in mind, I can't wait to see what a competently executed review and tear down youtube video will reveal when it is finally released to the market. 

[EDIT] After posting this missive, I decided to have a quick look for any FY6900 video reviews on youtube but, as previously, it was blissfully unaware such a device even existed. However, I did come across this interesting reminder as to why these Feeltech offerings are such stonking good value



 The Siglent SDG1032X Signal Generator is £360 from their UK agent with the SDG1062X another £80 to get the version that most closely resembles the 60MHz sine wave frequency spec of the FY6600-60M and the FY6800-60M models.

 You can compare the specs between the 32 and 62 models here:-

http://www.labtronix.co.uk/drupal/sites/default/files/sdg1000x/SDG1000X_DataSheet_DS0201X_E01A.pdf

 As for the Rigol DS1022 in that shoot out video, that sucks even more the the Siglent did which fell short in so many ways against the trusty Feeltech products we've all come to know and love/hate.

 That shoot out video was such an eye opener as to just how good a bargain these Feeltech signal/function generators actually are, I thought I'd provide a link to it as a reminder to those who nitpick criticise the FY66/68, forgetting completely that even brand named kit with prices that start at a minimum of five times higher have their own shortcomings and limitations which make the Feeltech kit superior in some aspects of their specifications (eg the inability to produce square wave outputs at 20Vpp beyond 5 and 10 MHz for the Rigol and Siglent respectively versus the FY6600 and 6800's 20MHz limits). Mind you, I wasn't impressed by the reviewer's use of a 70MHz BW 'scope and an unterminated BNC cable in his test setup.

 The next time you want to nitpick over the irritating use of mcroHertz and milliHertz units in the frequency display (having forgotten that you can cycle through the units on the 6600's rotary encoder's push button function or the 6800's "OK" button), just remind yourself that you've saved yourself at least 280 quid on a "Decent Signal Generator". If that pleasant thought fails to provide consolation, then you have to ask yourself "Why the f*ck did I waste my money on a "cheap 'n' cheerful" Feeltech generator in the first place?".

 Let's face it, the most intractable issue with the FY series of signal generators is their 4ns jitter on pulse and square waves which, quite frankly, are more a cosmetic issue in 'scope traces rather than of any real consequence to a properly designed digital process which should cheerfully take such modest amounts of jitter in its stride.

 For Christ's sake, the PC motherboard manufacturers have been offering a 'jitter' function on the clock signals for over a decade now under the label of "Spread Spectrum" taking full advantage of the logic circuits' inherent tolerance to jitter to minimise the impact of any RFI emissions that could otherwise interfere with other users of the radio spectrum.

 Obviously, there will be circumstances where this jitter will be a liability, demanding the spend of another 500 quid or more to run these more demanding test sequences. However, in a hobbyist context, the issue of jitter is less likely to arise. If it does, then the poor hobbyist is simply going to either have to use a cunning work around or else bite the bullet and track down a second hand 'bargain' that will serve this need.

 As a 'heads up', it seems to me that one cunning work around (to save spending 500 quid or more) would be to use the Sinc pulse output to drive a Schmitt triggered input gate or buffer of the appropriate logic family to match what you're testing since, like the sine wave output, this also seems to be free of this 4ns jitter which, unlike the sine wave, offers faster rise and fall times more suited to triggering pulses or square waves with well defined edges.

JBG

[radiolistener]

Sine waves don't have this jitter, so if you need a clock, try a sine wave. 

sine wave has exactly the same jitter. But sine wave has more slow slope, and this jitter is hidden behind slow slope. Since slope is too slow, amplitude change will be very small, so you will not see it in time domain. But you will see it on frequency domain.

If it hasn't already been said, the 4ns "jitter" is just the natural result of a 250 MSa/s fixed clock DDS putting out a square wave with a period that is not a multiple of 4ns. 

Such jitter will be "natural result" for DAC with fixed sample rate. But FY6900 has FPGA and can use any desired sample rate for DAC, so this is not the case for FY6900 hardware. FY6900 can produce signal with better jitter, just by using variable sample rate. Yeah it's a little bit more complicated, but it is possible and it's worth it. So, this jitter is just a software limitation in FPGA code and can be reduced by software patch.

[Johnny B Good]

Sine waves don't have this jitter, so if you need a clock, try a sine wave. 

sine wave has exactly the same jitter. But sine wave has more slow slope, and this jitter is hidden behind slow slope. Since slope is too slow, amplitude change will be very small, so you will not see it in time domain. But you will see it on frequency domain.

If it hasn't already been said, the 4ns "jitter" is just the natural result of a 250 MSa/s fixed clock DDS putting out a square wave with a period that is not a multiple of 4ns. 

Such jitter will be "natural result" for DAC with fixed sample rate. But FY6900 has FPGA and can use any desired sample rate for DAC, so this is not the case for FY6900 hardware. FY6900 can produce signal with better jitter, just by using variable sample rate. Yeah it's a little bit more complicated, but it is possible and it's worth it. So, this jitter is just a software limitation in FPGA code and can be reduced by software patch.

 Yes, you'd expect to see the same jitter effect on sine waves if you use a high enough frequency (10MHz 10Vpp setting driving into a 50R terminated cable - 5Vpp to the scope) and pick a fast timebase such as 10 or 5 ns per division but in actual fact you don't (at least not with the souped up FY6600-60M I'm using).

 I tried my best to track down a youtube video demonstrating and explaining this effect but, surprise surprise , to no fekin' avail, hence my running some tests of my own (now that I've gotten bored with waiting for the Sinc pulse to drag itself into phase with the next GPSDO rising edge of its 10MHz clock output at the rate of 20 minutes per transit).

 One of the unexpected benefits of going OTT in the FY6600 reference oscillator upgrade to a 10MHz OCXO with a five times multiplier chip displacing the original and execrable ten a dime smd 50MHz XO is being able to observe the 4ns jitter on a 10MHz square wave in slow motion when you detune from 10MHz by just 8mHz. 

 I've got the 'scope triggering ch2 from the GPSDO with the FY6600 feeding ch1 at an 8mHz offset from the exact 10MHz which otherwise hides this jitter through sheer synchronicity with the FPGA's 50MHz clock which is also used to generate the 250MHz clock which drives the DAC.

 I've dropped the timebase right down to 200ns per division and zoomed in on the section at the RHS of the display (1.04μs delay) with an effective 10ns per division on the zoomed view, allowing me to observe jitter of any sort some ten cycles away from the trigger point to amplify any accumulated jitter.

 I'm pleased to report that I can observe no signs of accumulated jitter which is a tribute to both the signal generator and the 'scope (a Siglent SDS 1202X-E btw). However, at this 8milliHertz offset, I can see the square wave slowly shuffle along from right to left one set of rising then falling flanks at a time at a cycle rate of 200mHz (a 5 second period). When it comes to observing the behaviour of sine and (surprisingly) triangle waves, there is absolutely no evidence of this 4ns jitter, just a continuous and smooth leftwards drift.

 A quick scan through all the other preloaded waveforms reveals that some 50% or more are likewise free of this 4ns jitter, including quite obviously, my favourite for 'scope trace frequency comparison, the Sinc-Pulse waveform.

 I won't waste any more electrons describing which do and which don't suffer this 4ns jitter effect, in part because ICBA but mostly so as not to spoil the surprise for anyone else who has replaced the shitty little smd XO with at least a half decent TCXO to endow their much modded FY6600s and FY6800s with at least sufficient frequency stability (if not accuracy - using a 10MHz NPL grade frequency reference isn't actually required for this exercise) to observe which waveforms are and aren't effected.

 For those who haven't bothered with such an upgrade - good news! It seems you're in luck. I've stopped triggering from the GPSDO and I can still observe the jitter in slow motion. The difference being that the lack of sideways drift means the square wave only shows the effect on the falling edge with the rising edge staying put despite being delayed some 1.04μs from the trigger point. However, I suspect the original XO chip may allow some jitter to creep in with this much delay. If this proves the case, you can simply observe at the trigger point without any large delay (you'll only lose out on observing the peculiar crabbing effect of triggering from a 10MHz reference whilst the generator is offset by 8mHz)

 Those comments about the FY6900 having a FPGA (they all do) which can be programmed to reduce jitter with a firmware patch, are rather intriguing. Do you have inside information on such a firmware update which Feeltech/Feelec have seen fit to make no mention of?

 Such a statement just makes me even more curious about what a properly conducted technical review will reveal. However, I won't be pre-ordering one on the rather tenuous basis that it might have such an enhancement alone.

JBG

[bdunham7]

Sine waves don't have this jitter, so if you need a clock, try a sine wave. 

sine wave has exactly the same jitter. But sine wave has more slow slope, and this jitter is hidden behind slow slope. Since slope is too slow, amplitude change will be very small, so you will not see it in time domain. But you will see it on frequency domain.

If it hasn't already been said, the 4ns "jitter" is just the natural result of a 250 MSa/s fixed clock DDS putting out a square wave with a period that is not a multiple of 4ns. 

Such jitter will be "natural result" for DAC with fixed sample rate. But FY6900 has FPGA and can use any desired sample rate for DAC, so this is not the case for FY6900 hardware. FY6900 can produce signal with better jitter, just by using variable sample rate. Yeah it's a little bit more complicated, but it is possible and it's worth it. So, this jitter is just a software limitation in FPGA code and can be reduced by software patch.

I didn't fully understand your explanation, but your conclusion is incorrect both in fact and in theory.  The slope of a sine wave is absolutely no impediment to viewing jitter.  I can frequency modulate a carrier with a square wave (or just use FSK, I suppose) and it shows up just fine viewing just a few cycles.  I'm observing the zero crossing which can't be hidden or obscured!  In fact, the FY6600 I have produces obvious 4ns jitter of a binary variety--either one way or the other but not in between--for square waves and rectangular pulses of a period that is not a multiple of 4ns.  OTOH, almost every other waveform, including triangle and sine, does not have this type of jitter no matter how I observe it--a few cycles, many cycles on zoom, FFT, you name it.

The theory is simple:  Nyquist says that as long as I have a sample rate that is 2x (2.5x in practice) of my bandwidth, I can accurately reproduce my sine wave of any frequency within the bandwidth.  The key here is that my samples can be at any point on the sine wave and can vary in amplitude.  So, for a 9.999MHz sine wave, I get about 25 samples per cycle, but their position and amplitude can vary as needed.  Nyquist also says that due to their infinite bandwidth, you can never accurately reproduce a square wave with sampling, almost sort of, the exception being if the period each half of the square wave is an exact multiple of the sampling period.  The key, again, here, is that in a simple DDS system, the amplitude of the output samples is constrained between high and low.  When sampling a sine wave, a slight shift in the time domain yields a slight shift in the amplitude.  With square, it is all or nothing.  Thus the 4ns 'jitter' that we see is a phenomenon limited to functions with sharp transitions--square waves, pulses, single-ended ramps and so on.

I haven't dissected my FY6600 so I don't know if your assertion that it has all the necessary hardware for a variable sample rate is true.  I suspect it isn't, although I wouldn't rule out someone being clever enough to make it happen.  This limitation is common among most lower-end sig-gens and I'm sure this model is cut to the bone to make their price point.  The one cheap, simple way that has occurred to me is to use linear interpolation where if there is a transition within the 4ns period, that sample is interpolated time-wise to at least put the edge in more or less the right place.  Since this unit has ~7ns rise times anyway, an occasional 8ns or so rise time with the zero crossing in the right place would look a whole lot better.

[maxwell3e10]

Until Agilent introduced Trueform technology in 2012 and other manufactures followed, most function generators suffered from the jitter problem if the frequency of a square waveform is not a multiple of the sample frequency.  So even the previous generation of Agilent generators, 33220 had a significant amount of jitter. The fact that you can now get a generator of similar performance for close to 1/100 of the price is quite impressive.

[bdunham7]

 Seriously, you'd be better off imho, getting hold of the 6800 instead of the 6900 (but that 40 quid 6600 is such a bargain and the specification so identical to the 6800 it's hard to resist).  At that price, I couldn't resist buying myself a 'spare' but the one I ordered just on four weeks ago now is supposed to be arriving no later than today. I'll believe that when I see it. Fortunately, I'm not in any great hurry.

JBG

Did you ever get your unit from HK?

[radiolistener]

I didn't fully understand your explanation, but your conclusion is incorrect both in fact and in theory.  The slope of a sine wave is absolutely no impediment to viewing jitter.

your theory is wrong. It doesn't matter what kind of waveform you're using, the jitter is always here. But square and triangle wave has more high frequency components which affected by jitter much more. The main reason why you don't notice jitter for sine wave and notice it for square wave is slow slope of the sine wave.

The jitter is nothing more than time axis error for waveform point. You can see on the picture below that this time error depends on voltage error and vice versa. These errors on time axis and voltage axis are linked together.




When the slope of waveform is slower, the voltage axis error will be smaller for the same jitter. And vice versa, when the slope of waveform is faster, the voltage error will be higher for the same jitter. When you looking at sine waveform on oscilloscope, it has too slow slope in order to notice voltage error caused by jitter.

But the jitter is still there, you're just using wrong instrument to detect it. If you will use spectrum analyzer, you will see that the jitter for sine wave and for square wave is the same.

The theory is simple

for a 9.999MHz sine wave, I get about 25 samples per cycle

you can never accurately reproduce a square wave with sampling

When sampling a sine wave, a slight shift in the time domain yields a slight shift in the amplitude.  With square, it is all or nothing.

Yes, the theory is simple, and there is the same theory for sine wave and for square wave. A slight shift on the time axis yields a slight shift on the amplitude axis. But square wave has faster slope and this "slight shift" is more visible on that slope.

Let's don't talk about infinite spectrum of square wave, we don't need ideal square wave. We're need just a good square wave with a low jitter.

This jitter happens when you're trying to generate frequency which is not multiple of DAC sample rate frequency. In such case your signal doesn't fit DAC aperture, and some points will have floating error. And it doesn't matter if you're trying to generate sine or square wave. They both will have this jitter.

The solution here is to change DAC sample rate, in order to properly fit your wave with DAC aperture. For example if you're want to generate 9.999 MHz, you can change DAC sample rate from 250 MHz to 249.975 MHz and this jitter will disappears, just because 249.975 MHz / 25 = exactly 9.999000 MHz.   Now the square wave exactly fits with DAC aperture and the reason for this jitter is removed.

The square wave will not be ideal, because it's spectrum is limited by analog bandwidth of the output amplifier and jitter of oscillator and different components (FPGA and DAC). But this jitter will be much more smaller and almost not noticeable.

This is not so easy to implement, because it needs to produce custom DAC sample rate and it should be low jitter. It requires to reconfigure PLL in FPGA at runtime, and it leads to use more complicated approach in FPGA software, but it is possible. The main complexity here for FPGA software is to get custom frequency with a low jitter.

Thus the 4ns 'jitter' that we see is a phenomenon limited to functions with sharp transitions--square waves, pulses, single-ended ramps and so on.

This 4 ns jitter is a result of fixed DAC sample rate. FY6600 has FPGA and there is not a big deal to use variable DAC sample rate. If you don't believe that FY6600 hardware allows to produce square wave with much-much lower jitter (almost not noticeable), you can check square wave at fequencies which are integer multiple of oscillator frequency. FY6600 already produces almost no jitter square wave at such frequencies 

[bdunham7]

What we have here is failure to communicate. 

So instead of refuting your arguments, I'll just show you some pictures. 

The waveforms and statistics should be self explanatory.  The FFTs are in order: 9.8MHz sine wave, 10MHz square, 9.8MHz square (there's your jitter) and lastly a 9.615384MHz square which corresponds to a 104ns period.  I don't have the 10MHz sine FFT somehow but it wasn't much different than the first FFT, just a little less noisy. Last photo is a 10MHz sine wave with 4ns variation in period from 100us to 104us (using FSK modulation).  FSK and jitter aren't necessarily indentical concepts, but it is just to show that 4ns of period difference is certainly visible.

[Johnny B Good]

Sine waves don't have this jitter, so if you need a clock, try a sine wave. 

sine wave has exactly the same jitter. But sine wave has more slow slope, and this jitter is hidden behind slow slope. Since slope is too slow, amplitude change will be very small, so you will not see it in time domain. But you will see it on frequency domain.

If it hasn't already been said, the 4ns "jitter" is just the natural result of a 250 MSa/s fixed clock DDS putting out a square wave with a period that is not a multiple of 4ns. 

Such jitter will be "natural result" for DAC with fixed sample rate. But FY6900 has FPGA and can use any desired sample rate for DAC, so this is not the case for FY6900 hardware. FY6900 can produce signal with better jitter, just by using variable sample rate. Yeah it's a little bit more complicated, but it is possible and it's worth it. So, this jitter is just a software limitation in FPGA code and can be reduced by software patch.

I didn't fully understand your explanation, but your conclusion is incorrect both in fact and in theory.  The slope of a sine wave is absolutely no impediment to viewing jitter.  I can frequency modulate a carrier with a square wave (or just use FSK, I suppose) and it shows up just fine viewing just a few cycles.  I'm observing the zero crossing which can't be hidden or obscured!  In fact, the FY6600 I have produces obvious 4ns jitter of a binary variety--either one way or the other but not in between--for square waves and rectangular pulses of a period that is not a multiple of 4ns.  OTOH, almost every other waveform, including triangle and sine, does not have this type of jitter no matter how I observe it--a few cycles, many cycles on zoom, FFT, you name it.

The theory is simple:  Nyquist says that as long as I have a sample rate that is 2x (2.5x in practice) of my bandwidth, I can accurately reproduce my sine wave of any frequency within the bandwidth.  The key here is that my samples can be at any point on the sine wave and can vary in amplitude.  So, for a 9.999MHz sine wave, I get about 25 samples per cycle, but their position and amplitude can vary as needed.  Nyquist also says that due to their infinite bandwidth, you can never accurately reproduce a square wave with sampling, almost sort of, the exception being if the period each half of the square wave is an exact multiple of the sampling period.  The key, again, here, is that in a simple DDS system, the amplitude of the output samples is constrained between high and low.  When sampling a sine wave, a slight shift in the time domain yields a slight shift in the amplitude.  With square, it is all or nothing.  Thus the 4ns 'jitter' that we see is a phenomenon limited to functions with sharp transitions--square waves, pulses, single-ended ramps and so on.

I haven't dissected my FY6600 so I don't know if your assertion that it has all the necessary hardware for a variable sample rate is true.  I suspect it isn't, although I wouldn't rule out someone being clever enough to make it happen.  This limitation is common among most lower-end sig-gens and I'm sure this model is cut to the bone to make their price point.  The one cheap, simple way that has occurred to me is to use linear interpolation where if there is a transition within the 4ns period, that sample is interpolated time-wise to at least put the edge in more or less the right place.  Since this unit has ~7ns rise times anyway, an occasional 8ns or so rise time with the zero crossing in the right place would look a whole lot better.

 Thank you bdunham7,

 That explanation neatly explains why the 4ns jitter is totally absent from sine waves and anything else based on sine waves. Whilst I had the wonderfully explained reasons why a bandwidth limited signal doesn't produce stair steps when digitised and converted back to analogue in this excellent video presentation in mind which, for anyone who hasn't already watched it, is well worth viewing:-



 I just had to run my own tests to confirm these facts for myself, just in case the function generator was doing something strange and wonderful in its processing of stored waveforms. The key to the matter of this sampling jitter on sharp edged pulses that you unearthed is the fact that they involve a theoretically infinitely fast transition between two levels at least once per cycle.

 This was precisely what I saw when trying successive waveforms one by one. Anything involving a sine curve such as all of the rectified sine wave examples whether full or half wave, as well as the triangle and the Sinc-pulse waveform, were completely devoid of the 4ns jitter that plagues all rectangular wave forms and ramps with an instant transition at the start or end of the ramping up or down period.

 Interestingly, I'm seeing rise/fall times of 3.8ns +/-200ps or so on the Sinc-Pulse and the buffered output from the GPSDO's OCXO. Considering such fast rise/fall times on the Sinc-Pulse waveform, it looks as though Feeltech (as they were calling themselves at the time) could have cheated their way out of this 4ns jitter issue rather like Siglent had done with their own dual channel DDS function generators (just take a look at their own 'scope traces demonstrating the elimination of the jitter of an earlier model - the 'cured trace' looks like all they've done is to smear out the rise/fall times to disguise the problem).

 If a sine based pulse can demonstrate such a fast rise and fall time as better than 4ns without any hint of the 4ns jitter that plagues the square wave, it strikes me that they could simply treat such waveforms as an imperfect square wave with a 4 or 5ns rise time limit before being processed by the DAC rather than have the DAC attempt the impossible task of generating an infinitely fast transition of which it has no control of in regard of its exact desired timing.

 Since there's a low pass anti-aliasing filter with something like a 75MHz cut off frequency[Edit; it might even be as high as 100MHz - still below the 125MHz Nyquist frequency in this case- since square waves as high as 30MHz are still recognisably a bandwidth limited square wave when displayed on a 200MHz BW 'scope] in the path, the highest "square wave" frequency you can hope to put out that still has a vague resemblance to such would be just 25MHz[Edit; 30MHz] at a pinch. Imposing a rise/fall time limit of 8ns would be the least of such a square wave's problems at that upper frequency limit so would 'cure the 4ns jitter without too much compromise. If it works for Siglent, then why not? Perhaps I'm taking too simplistic a view of the problem but the Sinc-Pulse evidence would suggest not.

 If the cure is as simple as I've hypothesised and Feelelec have applied a firmware update to do exactly that, then the new iteration of the FY6*** series may well be worth considering as an upgrade. However, if that were the case, you'd expect Feelelec to be boasting this feature rather than the 24Vpp in the 0 to 5MHz range feature of somewhat dubious worth.

 I've said this before but it will be interesting to see a full review of this 'new and improved' model when it finally does hit the market or preview samples are issued to selected and privileged reviewers.

JBG

[radiolistener]

So instead of refuting your arguments, I'll just show you some pictures. 

As you can see, your pictures with FFT (even despite the fact that it has too low resolution and a lot of aliases) shows that the jitter is present on both waveforms - sine wave and on sqare wave. You can see that jitter as a more taller "grass" and "Christmas Tree" around the fundamental component in frequency domain. 

And you can see that 10 MHz square wave has no jitter. I mean noticeable 4 ns jitter that we're talking about. Yes, it always has some small jitter, some picoseconds or something like that, but it is not so bad as 4 ns.

This is because 10 MHz can be taken with integer divider (with no fraction part) from used DAC sample rate frequency. 9.8 MHz cannot be taken with integer divider from DAC sample rate frequency, it leads to fraction part. This fraction part leads to floating error on time axis, which is nothing else than our 4 ns jitter on oscilloscope.

You can eliminate this jitter on 9.8 MHz square wave just by change DAC sample rate. For example, if you change DAC sample rate to 196 MHz, your 9.8 MHz square wave will be jitter free. Because 196 MHz / 20 = exactly 9.800000 MHz with no fraction part.

Do you still think that it's impossible to synthesize 196 MHz on FPGA PLL?

[Johnny B Good]

 Seriously, you'd be better off imho, getting hold of the 6800 instead of the 6900 (but that 40 quid 6600 is such a bargain and the specification so identical to the 6800 it's hard to resist).  At that price, I couldn't resist buying myself a 'spare' but the one I ordered just on four weeks ago now is supposed to be arriving no later than today. I'll believe that when I see it. Fortunately, I'm not in any great hurry.

JBG

Did you ever get your unit from HK?

 Nah, and it's now 10 days overdue on the latest of the estimated dates of delivery. I sent the dealer a message to alert them of the delay via Ebay's notification system a couple of days ago. I now see they did respond late Friday afternoon with the following message:

'dear customer, We sent the item by the ordinary mail way and it only has a little tracking information .Since you still haven’t received it till now, I think it may be delayed in transit or lost on the way. But please don’t worry, we will be fully responsible, and we will send you a new parcel for free. But if you receive two parcels finally, would you please refused one or pay for the second item ,is this fine with you? Many thanks! Best wishes '

 I'm a little dubious about being able to refuse a second parcel after the original or second parcel finally turns up. I only need the one 'spare generator', owning two 'spares' would, to my mind,  be gilding the lily somewhat. This is a situation I've never had to deal with before. Presumably refusing delivery on a second unwanted item is perfectly normal practice in these cases? 

 It might, for all I know turn up in Saturday's post and I'll be able to save the dealer the trouble of sending a second unit. Interestingly, that 99p order, after I discovered the Parcelmonitor web site to submit its tracking number to, has been languishing in customs processing, Hong Kong since the 1st of June and, apparently is still there as I type this reply.
The only thing to be said in its favour is that it isn't actually overdue on its latest delivery date (25/07/19).

 I'll report on the firmware version as soon as I get hold of my 'bargain signal generator', whenever that might be.

JBG

[radiolistener]

4ns jitter is totally absent from sine waves and anything else based on sine waves

this 4 ns IS PRESENT on sine wave, but you don't see it on oscilloscope, because sine wave has too slow slope. You're need to use higher frequency sine wave in order to see it on oscilloscope. Or just use spectrum analyzer, it will show you this jitter (as parasitic spectral components) for sine wave on any frequency.

This picture will explain you why this 4 ns jitter is present on sine wave, but you don't notice it on oscilloscope:

[bdunham7]

@ JBG:  What is your maximal delivery date?  Mine is Aug 07, with a range of Jun 26 to Aug 07 given.  If it goes over that maximal date, you need to file a not-received report with eBay and resolutely ignore any pleas from the seller to accept a second shipment or a refund through PayPal outside the eBay process. I've worried about non-shipment since day one.

@radiolistener:  I've no idea what to say.   I've clearly demonstrated the ability to see 4ns period deviation on a sine wave (last photo).  The FFTs are fine for what they are and pretty clearly show what I want them to.  Yes, there is jitter on all of the waveforms, but the 9.8MHz square wave clearly stands out both in the FFT and in the measurments.  And if you look at the statistics under the waveforms the 9.8MHz square wave is showing a 1.75ns width deviation and 160ps std deviation on period.  All the other period deviations are in the 10s of nanoseconds.  The deviation numbers on the square wave go up by a factor of 7-8 when you go from 10.0 to 9.8 MHz.  The number for the sine wave go up by maybe 30%, so maybe there are issues with sample interpolation producing distortion in the sine wave--but it doesn't have a 4ns problem. 

[radiolistener]

bdunham7, if you think that small voltage error due to this 4 ns jitter will not affects your measurements much, it's a delusion.

In theory such 14 bit DAC should produce 9.8 MHz sine wave with about SNR=86 dB (it takes into account average DAC DNL and effective DAC noise and zero jitter). This is what should be with zero jitter.

But jitter will leads to SNR degradation. For example 4 ns RMS jitter for 9.8 MHz sine wave will leads to SNR=12 dB.
The difference is 74 dB!

74 dB of dynamic range is lost just due to 4 ns jitter! And this is for sine wave. 

if you look at the statistics under the waveforms the 9.8MHz square wave is showing a 1.75ns width deviation and 160ps std deviation on period.

For calculations I assumed 14 bit DAC with average DNL = 0.41 LSB and effective output noise of DAC = 0.9 LSB.

The theory says that 160 ps RMS jitter for 9.8 MHz sine wave will leads to SNR = 40.1 dB.

This pretty well correspond to these parameters that we seen in reality for FY6600.

But the difference with zero jitter DAC is 45.91 dB!
The loss of 46 dB dynamic range is too much.

[bdunham7]

So look at the pictures and tell me how they agree or disagree with your theoretical explanations. 

[pantelei4]

this 4 ns IS PRESENT on sine wave, but you don't see it on oscilloscope, because sine wave has too slow slope.

dV/dT limited by output amplifier
At high frequency, the slope of the output meander and the sine is the same. But there is no 4 ns jitter visible on the sine, even at high sensitivity.

[radiolistener]

So look at the pictures and tell me how they agree or disagree with your theoretical explanations.

Theory predicts SNR = 40 dB at 9.8 MHz sine wave for RMS jitter 160 ps (it's your measurement for 9.8 MHz square wave).

Your picture shows a little worse performance, at 9.8 MHz SNR is about 25 dB or something like that.
The worse performance in reality can be explained by not enough precision of your equipment.
Probably RMS jitter is more than 160 ps at 9.8 MHz.
According to your pictures RMS jitter is about 900 ps.
And in overall my theoretical explanation pretty well corresponds with your pictures. 

[radiolistener]

At high frequency, the slope of the output meander and the sine is the same. But there is no 4 ns jitter visible on the sine, even at high sensitivity.

that's interesting information. May be this is because FPGA trying to apply interpolation for sine wave and the result is then filtered with analog bandwith, but for square wave it just puts max and min values with no interpolation?

Interpolated points is more close to real sine in comparison with min/max value with no interpolation. If so, then this is the second bug in the FPGA software.

Any other ideas how it is possible?

[pantelei4]

May be this is because FPGA trying to apply interpolation for sine wave and the result is then filtered with analog bandwith, but for square wave it just puts max and min values with no interpolation?

Yes, interpolation for the front of the meander is impossible and this is the max and min values

[radiolistener]

Yes, interpolation for the front of the meander is impossible and this is the max and min values

I think it is possible, but is more hard, we're need to take into account the actual analog bandwidth for calculations.
Because if we ignore analog bandwidth we will get much higher error.

[pantelei4]

I think it is possible, but is more hard, we're need to take into account the actual analog bandwidth for calculations.

Probably they do this in more advanced DDS, taking into account the bandwidth of the analog output, interpolation of the fronts of the meander occurs.

[radiolistener]

yeah, implementing such features requires a lot of math and more complicated software, also it makes sense to use better analog frontend, so it is not for entry level device

But may be sometimes we will see it in cheap FY7000 or something like that 

[pantelei4]

yeah, implementing such features requires a lot of math and more complicated software

It does not require, it is necessary only once to compile an interpolation table of the slope of the pulse fronts in accordance with the analog band
That's the whole secret of MagicPulse

[Johnny B Good]

@ JBG:  What is your maximal delivery date?  Mine is Aug 07, with a range of Jun 26 to Aug 07 given.  If it goes over that maximal date, you need to file a not-received report with eBay and resolutely ignore any pleas from the seller to accept a second shipment or a refund through PayPal outside the eBay process. I've worried about non-shipment since day one.

 24th of June till the 3rd of July. As I said, it was already a week overdue on the final date when I used Ebay's "Send a Request" to inform the dealer of the delay. The response two days later seems quite reasonable, especially after having a good night's sleep to refresh my rather tired state of mind when I first read it.

 As far as I can see, they're offering to send a second parcel straight away in the event that the original cannot be immediately located and accounted for in the postal system. Requesting that if a second parcel finally lands on my doorstep that I refuse it and ensure its return with the option to pay for it (presumably also at half price) if I so desire to have a second 'cheap spare'. Since one "cheap spare" is more than enough, I won't be availing myself of that option.

 It's obvious that they've chosen the cheapest, non tracked (presumably also uninsured) option by the cheapest carrier on the basis that such loss events are statistically rare enough to forego the expense of a tracked and insured posting option for it to be cheaper to resolve such failures by simply shipping out a replacement at their own cost rather than pay a higher premium to make the carrier take full responsibility for any such losses. It's known as 'Playing the Odds'.

 This is all fine and dandy, provided they remember to bribe their luckless customer into doing repeat business and not badmouth them for the additional delay on top of the already excruciating delay even when delivery times are actually met. I'll accept their offer but only on the basis that they offer some financial compensation for the late delivery and their assurance that the firmware is version 3.3 or above.

 I notice that they are now asking 80 quid for the FY6600-60M models (double the price I'd paid) so I'd rather receive the goods at that price or not at all. If I cancel the order, I'll lose out on my "Half price Bargain". Since I'm not in any desperate hurry to acquire a spare unit, it seems my best option is to accept their solution and hope they take my request for assurance of the firmware version and a modicum of recompense for the extra delay (33 to 50 percent off ) seriously. I haven't responded yet so I'll see what concessions I can wring out of them.

[EDIT]

 I've just sent this message via Ebay's request system.

Thank you for the offer. Before I accept, can you assure me that the item is not old stock cursed by firmware versions 3.0 and 3.1 which caused them to be rendered unusable? It needs to be at version 3.3 or above. Also, as is normal in these cases, will you be offering some discount by way of recompense for the inconvenience of this additional delay?

 Hopefully, I'll get a favourable response ("Nothing ventured, nothing gained." and all that...), and all under auspices of Ebay's "Send a Request" system which gives me the option to escalate it to Ebay on or after the 19th.

BTW, that little 99p pack of HC14s are still stuck in HK customs. They've been there since the 1st of June!!! However, the latest date of arrival is still some 12 days off so I can't do anything about that one just yet (it's still 'early days'... after six weeks!

JBG

[bdunham7]

I  think it pays to be a little more hard-hearted with sellers.  You have 30 days from the last delivery date to file INR, and some of these guys will say anything to try and run the clock out.  This is seller honghong20, right?  I haven't received mine nor you yours, so I think it is possible that no packages have been sent.  Talk of refusing packages is pretty strange--you should NEVER refuse a package according to eBay--and the seller wouldn't want to incur the return shipping charges that would likely exceed the value of the transaction.